From c72ebabab6e2d9a326cc9822dfecb7cdfda46458 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 Mar 2023 17:26:00 +0100 Subject: [PATCH] whoops ls010 not ls009. add paragraph about exceptional behaviour changes --- openpower/sv/rfc/ls010.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 15bf1fa8b..ba99bd601 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -1,4 +1,4 @@ -# RFC ls009 SVP64 Zero-Overhead Loop Prefix Subsystem +# RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem Credits and acknowledgements: @@ -53,6 +53,15 @@ sustain 100% throughput* |--------|--------------|--------------| | EXT09 | v3.1 Prefix | v3.0/1 Suffix | +Two apparent exceptions to the above hard rule exist: SV Branch-Conditional +operations and LD/ST-update "Post-Increment" Mode. Post-Increment +was considered sufficiently high priority (significantly reducing hot-loop +instruction count) that one bit in the Prefix is reserved for it. +Vectorised Branch-Conditional operations "embed" the original Scalar +Branch-Conditional behaviour into a much more advanced variant that +is highly suited to High-Performance Computation (HPC), Supercomputing, +and parallel GPU Workloads. + Subset implementations in hardware are permitted, as long as certain rules are followed, allowing for full soft-emulation including future revisions. Compliancy Subsets exist to ensure minimum levels of binary -- 2.30.2