From c73f3ba39e2051aebcf39c1669c10c9dfa86bdc7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 6 Nov 2018 08:20:54 +0000 Subject: [PATCH] expand architectural requirements page --- 3d_gpu/microarchitecture.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 60756b716..92e614c22 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -6,11 +6,20 @@ each core with full 4-wide SIMD-style predicated ALUs * 6GFLOPS single-precision FP * 128 64-bit FP and 128 64-bit INT register files -* RV64GC compliance +* RV64GC compliance for running full GNU/Linux-based OS +* SimpleV compliance +* xBitManip (required for VPU and ideal for predication) * 4-lane 1Rx1W SRAMs for registers numbered 32 and above; Multi-R x Multi-W for registers 1-31. TODO: consider 2R for registers to be used as predication targets if >= 32. +* Potentially: Lane-swapping / crossing / data-multiplexing + bus on register data +* Potentially: Registers subdivided into 16-bit, to match + elwidth down to 16-bit (for FP16). 8-bit elwidth only + goes down as far as twin-SIMD (with predication). This + requires registers to have extra hidden bits: register + x30 is now "x30:0+x30.1+x30.2+x30.3". have to discuss. # Conversation Notes -- 2.30.2