From c745b102474f9102e811d95220c2dd0488b20afe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 24 Jan 2020 15:04:50 +0000 Subject: [PATCH] debug eq partition --- src/ieee754/part/test/test_partsig.py | 25 +++++++++++++++++-------- src/ieee754/part_cmp/equal.py | 24 +++++++++++++++++++----- 2 files changed, 36 insertions(+), 13 deletions(-) diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index 32382117..5e003c68 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -28,7 +28,7 @@ class TestAddMod(Elaboratable): self.a = PartitionedSignal(partpoints, width) self.b = PartitionedSignal(partpoints, width) self.add_output = Signal(width) - self.eq_output = Signal(len(partpoints)) + self.eq_output = Signal(len(partpoints)+1) def elaborate(self, platform): m = Module() @@ -79,7 +79,7 @@ class TestPartitionPoints(unittest.TestCase): yield part_mask.eq(0b1111) yield from test_add("4-bit", 0xF000, 0x0F00, 0x00F0, 0x000F) - def test_eq(msg_prefix, *mask_list): + def test_eq(msg_prefix, *maskbit_list): for a, b in [(0x0000, 0x0000), (0x1234, 0x1234), (0xABCD, 0xABCD), @@ -90,19 +90,28 @@ class TestPartitionPoints(unittest.TestCase): yield module.a.eq(a) yield module.b.eq(b) yield Delay(0.1e-6) + # convert to mask_list + mask_list = [] + for b in maskbit_list: + v = 0 + for i in range(4): + if b & (1< 0x{y:X} != 0x{outval:X}" - self.assertEqual(y, outval, msg) + f" => 0x{y:X} != 0x{outval:X}, masklist %s" + self.assertEqual(y, outval, msg % str(maskbit_list)) yield part_mask.eq(0) - yield from test_eq("16-bit", 0xFFFF) + yield from test_eq("16-bit", 0b1111) yield part_mask.eq(0b10) - yield from test_eq("8-bit", 0xFF00, 0x00FF) + yield from test_eq("8-bit", 0b1100, 0b0011) yield part_mask.eq(0b1111) - yield from test_eq("4-bit", 0xF000, 0x0F00, 0x00F0, 0x000F) + yield from test_eq("4-bit", 0b1000, 0b0100, 0b0010, 0b0001) sim.add_process(async_process) sim.run() diff --git a/src/ieee754/part_cmp/equal.py b/src/ieee754/part_cmp/equal.py index e680015d..7d5cd5a7 100644 --- a/src/ieee754/part_cmp/equal.py +++ b/src/ieee754/part_cmp/equal.py @@ -22,7 +22,7 @@ class PartitionedEq(Elaboratable): self.a = Signal(width, reset_less=True) self.b = Signal(width, reset_less=True) self.partition_points = PartitionPoints(partition_points) - self.mwidth = len(self.partition_points) + self.mwidth = len(self.partition_points)+1 self.output = Signal(self.mwidth, reset_less=True) if not self.partition_points.fits_in_width(width): raise ValueError("partition_points doesn't fit in width") @@ -33,13 +33,27 @@ class PartitionedEq(Elaboratable): # make a series of "eqs", splitting a and b into partition chunks eqs = Signal(self.mwidth, reset_less=True) eql = [] - keys = list(self.partition_points.keys()) - for i in range(len(keys)-1): - start, end = keys[i], keys[i+1] + keys = list(self.partition_points.keys()) + [self.width] + start = 0 + for i in range(len(keys)): + end = keys[i] eql.append(self.a[start:end] == self.b[start:end]) + start = end # for next time round loop m.d.comb += eqs.eq(Cat(*eql)) # now, based on the partition points, create the (multi-)boolean result - m.d.comb += self.output.eq(eqs) # TODO: respect partition points + eqsigs = [] + for i in range(self.mwidth): + eqsig = Signal(self.mwidth, name="eqsig%d"%i, reset_less=True) + if i == 0: + m.d.comb += eqsig.eq(eqs[i]) + else: + ppt = self.partition_points[keys[i-1]] + m.d.comb += eqsig.eq(eqs[i] & ppt & eqsigs[i-1]) + eqsigs.append(eqsig) + print ("eqsigs", eqsigs, self.output.shape()) + # XXX moo?? something going on here + for i in range(self.mwidth): + m.d.comb += self.output[i].eq(eqsigs[i]) return m -- 2.30.2