From c74e3015f1fe553b9120413c02ec89f9150fb423 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 1 Aug 2021 00:40:25 +0200 Subject: [PATCH] Fix various imports in src/unused/ Fixes: 1abb7996 ("move unused out of soc directory") --- src/unused/TLB/PermissionValidator.py | 2 +- src/unused/TLB/ariane/test/test_plru.py | 2 +- src/unused/TLB/ariane/test/test_ptw.py | 2 +- src/unused/TLB/ariane/test/test_tlb.py | 2 +- src/unused/TLB/ariane/test/test_tlb_content.py | 2 +- src/unused/TLB/ariane/tlb.py | 6 +++--- src/unused/TLB/ariane/tlb_content.py | 2 +- src/unused/TLB/test/test_LFSR2.py | 2 +- src/unused/TLB/test/test_address_encoder.py | 2 +- src/unused/TLB/test/test_cam.py | 2 +- src/unused/TLB/test/test_cam_entry.py | 2 +- src/unused/TLB/test/test_permission_validator.py | 2 +- src/unused/TLB/test/test_pte_entry.py | 2 +- src/unused/TLB/test/test_set_associative_cache.py | 2 +- src/unused/TLB/test/test_tlb.py | 2 +- src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py | 2 +- src/unused/iommu/axi_rab/test/test_slice_top.py | 2 +- src/unused/simulator/test_sim.py | 2 +- 18 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/unused/TLB/PermissionValidator.py b/src/unused/TLB/PermissionValidator.py index 5bc90b2f..19c8618d 100644 --- a/src/unused/TLB/PermissionValidator.py +++ b/src/unused/TLB/PermissionValidator.py @@ -1,7 +1,7 @@ from nmigen import Module, Signal, Elaboratable from nmigen.cli import main -from soc.TLB.PteEntry import PteEntry +from unused.TLB.PteEntry import PteEntry class PermissionValidator(Elaboratable): diff --git a/src/unused/TLB/ariane/test/test_plru.py b/src/unused/TLB/ariane/test/test_plru.py index 9222d796..92b4efe0 100644 --- a/src/unused/TLB/ariane/test/test_plru.py +++ b/src/unused/TLB/ariane/test/test_plru.py @@ -1,5 +1,5 @@ import sys -from soc.TLB.ariane.plru import PLRU +from unused.TLB.ariane.plru import PLRU from nmigen.compat.sim import run_simulation diff --git a/src/unused/TLB/ariane/test/test_ptw.py b/src/unused/TLB/ariane/test/test_ptw.py index 39697566..0fcd7682 100644 --- a/src/unused/TLB/ariane/test/test_ptw.py +++ b/src/unused/TLB/ariane/test/test_ptw.py @@ -1,5 +1,5 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.ariane.ptw import PTW, PTE +from unused.TLB.ariane.ptw import PTW, PTE # unit was changed, test needs to be changed diff --git a/src/unused/TLB/ariane/test/test_tlb.py b/src/unused/TLB/ariane/test/test_tlb.py index e1b17b8b..a50eeb65 100644 --- a/src/unused/TLB/ariane/test/test_tlb.py +++ b/src/unused/TLB/ariane/test/test_tlb.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.ariane.tlb import TLB +from unused.TLB.ariane.tlb import TLB def set_vaddr(addr): diff --git a/src/unused/TLB/ariane/test/test_tlb_content.py b/src/unused/TLB/ariane/test/test_tlb_content.py index 1bc60d88..c16e2c76 100644 --- a/src/unused/TLB/ariane/test/test_tlb_content.py +++ b/src/unused/TLB/ariane/test/test_tlb_content.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.ariane.tlb_content import TLBContent +from unused.TLB.ariane.tlb_content import TLBContent from soc.TestUtil.test_helper import assert_op, assert_eq diff --git a/src/unused/TLB/ariane/tlb.py b/src/unused/TLB/ariane/tlb.py index 72b67a2d..c16840bb 100644 --- a/src/unused/TLB/ariane/tlb.py +++ b/src/unused/TLB/ariane/tlb.py @@ -29,9 +29,9 @@ from nmigen import Signal, Module, Cat, Const, Array, Elaboratable from nmigen.cli import verilog, rtlil from nmigen.lib.coding import Encoder -from soc.TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH -from soc.TLB.ariane.plru import PLRU -from soc.TLB.ariane.tlb_content import TLBContent +from unused.TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH +from unused.TLB.ariane.plru import PLRU +from unused.TLB.ariane.tlb_content import TLBContent TLB_ENTRIES = 8 diff --git a/src/unused/TLB/ariane/tlb_content.py b/src/unused/TLB/ariane/tlb_content.py index bfd17c13..84ba219b 100644 --- a/src/unused/TLB/ariane/tlb_content.py +++ b/src/unused/TLB/ariane/tlb_content.py @@ -1,6 +1,6 @@ from nmigen import Signal, Module, Cat, Const, Elaboratable -from soc.TLB.ariane.ptw import TLBUpdate, PTE +from unused.TLB.ariane.ptw import TLBUpdate, PTE class TLBEntry: diff --git a/src/unused/TLB/test/test_LFSR2.py b/src/unused/TLB/test/test_LFSR2.py index 33208f83..cd74c462 100644 --- a/src/unused/TLB/test/test_LFSR2.py +++ b/src/unused/TLB/test/test_LFSR2.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: LGPL-2.1-or-later # See Notices.txt for copyright information -from soc.TLB.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3 +from unused.TLB.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3 from nmigen.back.pysim import Simulator, Delay, Tick import unittest diff --git a/src/unused/TLB/test/test_address_encoder.py b/src/unused/TLB/test/test_address_encoder.py index 70d435d6..72880dd9 100644 --- a/src/unused/TLB/test/test_address_encoder.py +++ b/src/unused/TLB/test/test_address_encoder.py @@ -1,5 +1,5 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.AddressEncoder import AddressEncoder +from unused.TLB.AddressEncoder import AddressEncoder from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op diff --git a/src/unused/TLB/test/test_cam.py b/src/unused/TLB/test/test_cam.py index d11cd974..a0381683 100644 --- a/src/unused/TLB/test/test_cam.py +++ b/src/unused/TLB/test/test_cam.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.Cam import Cam +from unused.TLB.Cam import Cam from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op diff --git a/src/unused/TLB/test/test_cam_entry.py b/src/unused/TLB/test/test_cam_entry.py index 961445b6..80901ca5 100644 --- a/src/unused/TLB/test/test_cam_entry.py +++ b/src/unused/TLB/test/test_cam_entry.py @@ -1,7 +1,7 @@ from nmigen.compat.sim import run_simulation from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op -from soc.TLB.CamEntry import CamEntry +from unused.TLB.CamEntry import CamEntry # This function allows for the easy setting of values to the Cam Entry # Arguments: diff --git a/src/unused/TLB/test/test_permission_validator.py b/src/unused/TLB/test/test_permission_validator.py index b52b5459..94e99c10 100644 --- a/src/unused/TLB/test/test_permission_validator.py +++ b/src/unused/TLB/test/test_permission_validator.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.PermissionValidator import PermissionValidator +from unused.TLB.PermissionValidator import PermissionValidator from soc.TestUtil.test_helper import assert_op diff --git a/src/unused/TLB/test/test_pte_entry.py b/src/unused/TLB/test/test_pte_entry.py index 51b3dcf0..390a94ec 100644 --- a/src/unused/TLB/test/test_pte_entry.py +++ b/src/unused/TLB/test/test_pte_entry.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.PteEntry import PteEntry +from unused.TLB.PteEntry import PteEntry from soc.TestUtil.test_helper import assert_op diff --git a/src/unused/TLB/test/test_set_associative_cache.py b/src/unused/TLB/test/test_set_associative_cache.py index edec055b..9b48bb03 100644 --- a/src/unused/TLB/test/test_set_associative_cache.py +++ b/src/unused/TLB/test/test_set_associative_cache.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.SetAssociativeCache import SetAssociativeCache +from unused.TLB.SetAssociativeCache import SetAssociativeCache from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op diff --git a/src/unused/TLB/test/test_tlb.py b/src/unused/TLB/test/test_tlb.py index 38656623..e925c62d 100644 --- a/src/unused/TLB/test/test_tlb.py +++ b/src/unused/TLB/test/test_tlb.py @@ -3,7 +3,7 @@ from nmigen.compat.sim import run_simulation -from soc.TLB.TLB import TLB +from unused.TLB.TLB import TLB from soc.TestUtil.test_helper import assert_op, assert_eq diff --git a/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py b/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py index 8d23ef05..161daa1b 100644 --- a/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py +++ b/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py @@ -1,4 +1,4 @@ -from ram_tp_write_first import ram_tp_write_first +from ..ram_tp_write_first import ram_tp_write_first from nmigen.compat.sim import run_simulation import sys sys.path.append("../") diff --git a/src/unused/iommu/axi_rab/test/test_slice_top.py b/src/unused/iommu/axi_rab/test/test_slice_top.py index c234b908..50f3321e 100644 --- a/src/unused/iommu/axi_rab/test/test_slice_top.py +++ b/src/unused/iommu/axi_rab/test/test_slice_top.py @@ -2,7 +2,7 @@ from nmigen.compat.sim import run_simulation import sys sys.path.append("../") # sys.path.append("../../../TestUtil") -from slice_top import slice_top +from ..slice_top import slice_top def tbench(dut): yield diff --git a/src/unused/simulator/test_sim.py b/src/unused/simulator/test_sim.py index 0a26380c..3b254997 100644 --- a/src/unused/simulator/test_sim.py +++ b/src/unused/simulator/test_sim.py @@ -2,7 +2,7 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay from nmigen.test.utils import FHDLTestCase import unittest -from soc.simulator.internalop_sim import InternalOpSimulator +from unused.simulator.internalop_sim import InternalOpSimulator from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel, -- 2.30.2