From c75787a008e94b8810892d8407b19cc64f89f3f5 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 9 Sep 2022 15:42:08 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls001/discussion.mdwn | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/rfc/ls001/discussion.mdwn b/openpower/sv/rfc/ls001/discussion.mdwn
index 79aebafc5..b16d801ab 100644
--- a/openpower/sv/rfc/ls001/discussion.mdwn
+++ b/openpower/sv/rfc/ls001/discussion.mdwn
@@ -1,6 +1,30 @@
 # potential opcode allocations
 
-discussion on ways to allocate scalar and svp64 opcodes
+discussion on ways to allocate scalar and svp64 opcodes.
+the first requirement is:
+
+* 75% of one major opcode for SVP64 (25%) SVP64-Single (25%)
+  SVP64-Reserved (25%)
+* 75% of one major opcode for grevluti crternlogi ternlogi (again each 25%)
+* 75% of one major opcode for xpermi fmvis fishmv bmrevi mv.swizzle etc.
+
+the additional requirements are:
+
+* all of the scalar operations must be Vectoriseable
+* all of the scalar operations must be in a 32-bit encoding (not prefixed-prefixed)
+
+# use 75% of QTY 3 MAJOR ops
+
+(for completeness: this idea is too much)
+
+there are a number of areas as candidates:
+
+* EXT006 (75%)
+* EXT005 (100%)
+* EXT009 (100%)
+
+However unfortunately as this would be the entire available
+32-bit Major opcodes used up, it is not viable.
 
 # major old/new scalar/vec
 
-- 
2.30.2