From c763fc2458b11453b26d802335a31abbc491ed7a Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Wed, 8 Jul 2020 12:48:32 +0200 Subject: [PATCH] Fix clock input In Micron's DDR3 model code, the clock is delayed and recreated as diff_ck from ck and ck_n. The clock is reconstituted by updating diff_ck on every positive edge of ck and ck_n. Having ck_n set as 0 would mean diff_ck being equal to a constant 1. --- gram/simulation/simsoctb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index f855a8b..4c1cabf 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -51,7 +51,7 @@ module simsoctb; ddr3 ram_chip ( .rst_n(1'b1), .ck(dram_ck), - .ck_n(1'b0), + .ck_n(~dram_ck), .cke(dram_cke), .cs_n(1'b0), .ras_n(dram_ras_n), -- 2.30.2