From c787b8d2a16d5e2950f209b1fcbec6e6c0388845 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Fri, 24 Jan 2020 15:17:44 +0100 Subject: [PATCH] aco/gfx10: Fix VcmpxExecWARHazard mitigation. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The SOPP instruction shouldn't have a definition, and its block should be set to -1 in order to prevent it from being recognized as a branch. Also fix a typo in the readme. Fixes: d6dfce02d074d615a3b88a3fccd8ee8c7e13c010 Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Tested-by: Marge Bot Part-of: --- src/amd/compiler/README.md | 1 - src/amd/compiler/aco_insert_NOPs.cpp | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/amd/compiler/README.md b/src/amd/compiler/README.md index 822ecd79cbc..7c7e68f458e 100644 --- a/src/amd/compiler/README.md +++ b/src/amd/compiler/README.md @@ -154,7 +154,6 @@ A VALU instruction or an `s_waitcnt vmcnt(0)` between the two instructions. Triggered by: An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR. -Despite LLVM Mitigated by: Any non-SOPP SALU instruction (except `s_setvskip`, `s_version`, and any non-lgkmcnt `s_waitcnt`). diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp index b9eaaed96db..689d5e25acc 100644 --- a/src/amd/compiler/aco_insert_NOPs.cpp +++ b/src/amd/compiler/aco_insert_NOPs.cpp @@ -491,9 +491,9 @@ void handle_instruction_gfx10(Program *program, NOP_ctx_gfx10 &ctx, aco_ptr depctr{create_instruction(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 1)}; + aco_ptr depctr{create_instruction(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)}; depctr->imm = 0xfffe; - depctr->definitions[0] = Definition(sgpr_null, s1); + depctr->block = -1; new_instructions.emplace_back(std::move(depctr)); } else if (instr_writes_sgpr(instr)) { /* Any VALU instruction that writes an SGPR mitigates the problem */ -- 2.30.2