From c7895c3f165244aefadd6a7a119097fa498736d5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 19:07:32 +0100 Subject: [PATCH] comment DecodeCRIn and DecodeCROut, gratuitously --- src/soc/decoder/power_decoder2.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index abea6e77..16f47b40 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -268,7 +268,11 @@ class DecodeOE(Elaboratable): return m class DecodeCRIn(Elaboratable): - """Decodes input CR from instruction""" + """Decodes input CR from instruction + + CR indices - insn fields - (not the data *in* the CR) require only 3 + bits because they refer to CR0-CR7 + """ def __init__(self, dec): self.dec = dec @@ -310,8 +314,13 @@ class DecodeCRIn(Elaboratable): return m + class DecodeCROut(Elaboratable): - """Decodes input CR from instruction""" + """Decodes input CR from instruction + + CR indices - insn fields - (not the data *in* the CR) require only 3 + bits because they refer to CR0-CR7 + """ def __init__(self, dec): self.dec = dec @@ -343,6 +352,7 @@ class DecodeCROut(Elaboratable): return m + class XerBits: def __init__(self): self.ca = Signal(2, reset_less=True) @@ -390,8 +400,8 @@ class Decode2ToExecute1Type(RecordObject): self.invert_out = Signal(reset_less=True) self.input_carry = Signal(CryIn, reset_less=True) self.output_carry = Signal(reset_less=True) - self.input_cr = Signal(reset_less=True) - self.output_cr = Signal(reset_less=True) + self.input_cr = Signal(reset_less=True) # instr. has a CR as input + self.output_cr = Signal(reset_less=True) # instr. has a CR as output self.is_32bit = Signal(reset_less=True) self.is_signed = Signal(reset_less=True) self.insn = Signal(32, reset_less=True) -- 2.30.2