From c7a78997ccbfd2315997733c9ccabc85c7555605 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 21 May 2023 23:35:50 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index a33ecf23c..9e6122686 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -1,5 +1,9 @@ # SV Load and Store +This section describes how Standard Load/Store Defined Words are exploited as +Element-level Load/Stores and augmented to create direct equivalents of +Vector Load/Store instructions. + Links: @@ -11,7 +15,6 @@ Links: * * * [[ldst/discussion]] - ## Rationale @@ -39,6 +42,7 @@ modes typically found in *all* Scalable Vector ISAs, without changing the behaviour of the underlying Base (Scalar) v3.0B operations in any way. (The sole apparent exception is Post-Increment Mode on LD/ST-update instructions) + ## Modes overview @@ -49,6 +53,7 @@ a number of different modes: * **element strided** - sequential but regularly offset, with gaps * **vector indexed** - vector of base addresses and vector of offsets * **Speculative Fault-first** - where it makes sense to do so +* **Data-Dependent Fail-First** - Conditional truncation of Vector Length * **Structure Packing** - covered in SV by [[sv/remap]] and Pack/Unpack Mode. *Despite being constructed from Scalar LD/ST none of these Modes exist @@ -124,7 +129,7 @@ The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE` | 0 | 1 | 2 | 3 4 | description | |---|---| --- |---------|--------------------------- | |els| 0 | PI | zz LF | post-increment and Fault-First | -|VLi| 1 | inv | CR-bit | ffirst CR sel | +|VLi| 1 | inv | CR-bit | Data-Dependent ffirst CR sel | The `els` bit is only relevant when `RA.isvec` is clear: this indicates whether stride is unit or element: @@ -177,8 +182,8 @@ but are the same `RM.MODE` bits (19:23 of `RM`): | 0 | 1 | 2 | 3 4 | description | |---|---| --- |---------|--------------------------- | -|els| 0 | PI | zz SEA | simple mode | -|VLi| 1 | inv | CR-bit | ffirst CR sel | +|els| 0 | PI | zz SEA | post-increment and Fault-First | +|VLi| 1 | inv | CR-bit | Data-Dependent ffirst CR sel | Vector Indexed Strided Mode is qualified as follows: -- 2.30.2