From c7aaa88f5807c7d49346b43b830a9826c52061ee Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Thu, 26 Nov 2020 22:30:48 -0500 Subject: [PATCH] machxo2: Add passing fsm, mux, and shifter tests. --- tests/arch/machxo2/fsm.ys | 15 +++++++++++++ tests/arch/machxo2/mux.ys | 40 +++++++++++++++++++++++++++++++++++ tests/arch/machxo2/shifter.ys | 10 +++++++++ 3 files changed, 65 insertions(+) create mode 100644 tests/arch/machxo2/fsm.ys create mode 100644 tests/arch/machxo2/mux.ys create mode 100644 tests/arch/machxo2/shifter.ys diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys new file mode 100644 index 000000000..847a61161 --- /dev/null +++ b/tests/arch/machxo2/fsm.ys @@ -0,0 +1,15 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-max 16 t:LUT4 +select -assert-count 6 t:FACADE_FF +select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys new file mode 100644 index 000000000..0cfc365bd --- /dev/null +++ b/tests/arch/machxo2/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 12 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys new file mode 100644 index 000000000..87fdab0fa --- /dev/null +++ b/tests/arch/machxo2/shifter.ys @@ -0,0 +1,10 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:FACADE_FF +select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D -- 2.30.2