From c7ae26be17d814e05023455eeb0a2b190b319e8e Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 11 Mar 2020 07:34:18 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/decoder.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3d_gpu/architecture/decoder.mdwn b/3d_gpu/architecture/decoder.mdwn
index 0f7231ea3..576931bc1 100644
--- a/3d_gpu/architecture/decoder.mdwn
+++ b/3d_gpu/architecture/decoder.mdwn
@@ -6,7 +6,7 @@ Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb
 
 # POWER
 
-The decoder has been written in python, to parse straight CSV files and othrr information taken directly from the Power ISA Standards PDF files. This significantly reduces the possibility of manual transcription errors and greatly reduces code size.  Based on Anton Blanchard's excellent microwatt design, these tables are in [[openpower/isatables]] which includes links to doenload the csv files.
+The decoder has been written in python, to parse straight CSV files and other information taken directly from the Power ISA Standards PDF files. This significantly reduces the possibility of manual transcription errors and greatly reduces code size.  Based on Anton Blanchard's excellent microwatt design, these tables are in [[openpower/isatables]] which includes links to doenload the csv files.
 
 The top level decoder object recursively drops through progressive levels of case statement groups, covering additional portions of the incoming instruction bits.  More on this is outlined here <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/004882.html>
 
-- 
2.30.2