From c7c72bd197a4502bfb948b42b16907a5f81de5c3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 12 Dec 2020 12:23:07 +0000 Subject: [PATCH] --- .../sv/svp_rewrite/svp64/discussion.mdwn | 26 +++++++++++++------ 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 1b03c6a54..33236c63e 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -24,16 +24,17 @@ twin predication and twin elwidth overrides is extremely important to have to be something like: -| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 20 | -| ----- | --- | --- | ---- | ---- | ----- | ----- | ----- | -| subvl | sew | dew | ptyp | psrc | pdst | vspec | sat | +| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 20 | +| ----- | --- | --- | ---- | ---- | ----- | ----- | ------ | +| subvl | sew | dew | ptyp | psrc | pdst | vspec | zmode | * subvl - 1 to 4 scalar / vec2 / vec3 / vec4 * sew / dew - DEFAULT / 8 / 16 /32 element width * ptyp - predication INT / CR * psrc / pdst - predicate mask selector and inversion * vspec - 3 bit src / dest scalar-vector extension -* sat: 2 bit s/u +* zmode: 2 bit src pred zero mode, dest pred zero mode +* ffirst: 3 bit. EN and CR index bit. ## twin predication, CR based. @@ -51,16 +52,25 @@ With different bits being selectable (CR[0..3]) starting from the same CR makes these are of the form res = op(src1, src2, ...) -| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 20 | -| ----- | --- | --- | ---- | ---- | ----- | ----- | -| subvl | sew | dew | ptyp | pred | vspec | sat | +| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 23 | +| ----- | --- | --- | ---- | ---- | ----- | ------ | +| subvl | sew | dew | ptyp | pred | vspec | mode | * subvl - 1 to 4 scalar / vec2 / vec3 / vec4 * sew / dew - DEFAULT / 8 / 16 /32 element width * ptyp - predication INT / CR * pred - predicate mask selector and inversion * vspec - 2/3 bit src / dest scalar-vector extension -* sat: 2 bit s/u +* mode - 5 bit + +Mode + + 0 1 2 3 4 description + ------------------ + 0 0 0 0 0 nothing + 0 1 N sat mode: N=0/1 u/s + 1 0 inv CR bit Rc=1: ffirst CR sel + 1 0 zero Rc=0: pred zero mode For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits. -- 2.30.2