From c7e1f71fd11e2009fd543ca7c036e7756e293a37 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Thu, 13 Aug 2020 12:01:11 -0700 Subject: [PATCH] mem_types.py add more types from common.vhdl --- src/soc/experiment/mem_types.py | 44 +++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py index bed4fffe..05e06388 100644 --- a/src/soc/experiment/mem_types.py +++ b/src/soc/experiment/mem_types.py @@ -96,8 +96,52 @@ class DcacheToMmuType(RecordObject): # end record; class MmuToIcacheType(RecordObject): def __init__(self): + super().__init__() self.tlbld = Signal() self.tlbie = Signal() self.doall = Signal() self.addr = Signal(64) self.pte = Signal(64) + +# type Loadstore1ToDcacheType is record +# valid : std_ulogic; +# load : std_ulogic; -- is this a load +# dcbz : std_ulogic; +# nc : std_ulogic; +# reserve : std_ulogic; +# virt_mode : std_ulogic; +# priv_mode : std_ulogic; +# addr : std_ulogic_vector(63 downto 0); +# data : std_ulogic_vector(63 downto 0); +# byte_sel : std_ulogic_vector(7 downto 0); +# end record; +class LoadStore1ToDcacheType(RecordObject): + def __init__(self): + super().__init__() + self.valid = Signal() + self.load = Signal() # this is a load + self.dcbz = Signal() + self.nc = Signal() + self.nc = Signal() + self.reserve = Signal() + self.virt_mode = Signal() + self.priv_mode = Signal() + self.addr = Signal() + self.data = Signal() + self.byte_sel = Signal() + +# type DcacheToLoadstore1Type is record +# valid : std_ulogic; +# data : std_ulogic_vector(63 downto 0); +# store_done : std_ulogic; +# error : std_ulogic; +# cache_paradox : std_ulogic; +# end record; +class DcacheToLoadStore1Type(RecordObject): + def __init__(self): + super().__init__() + self.valid = Signal() + self.data = Signal() + self.store_done = Signal() + self.error = Signal() + self.cache_paradox = Signal() -- 2.30.2