From c7e36acbe98fb858274e0f86b78c1b299d1a3059 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 8 Apr 2022 18:46:12 +0100
Subject: [PATCH] add read of SYSCON and entry for SPIFlash

---
 coldboot/coldboot.c | 43 +++++++++++++++++++++++++++++++++++--------
 src/ls2.py          |  6 ++++--
 2 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index e9bce65..ae612b5 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -66,10 +66,10 @@ uint32_t gram_read(const struct gramCtx *ctx, void *addr) {
 	uint32_t dword;
 
 	puts("gram_read: ");
-	uart_writeuint32(addr);
-	dword = readl(addr);
+	uart_writeuint32((unsigned long)addr);
+	dword = readl((unsigned long)addr);
 	puts(": ");
-	uart_writeuint32(dword);
+	uart_writeuint32((unsigned long)dword);
 	puts("\n");
 
 	return dword;
@@ -77,10 +77,10 @@ uint32_t gram_read(const struct gramCtx *ctx, void *addr) {
 
 int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
 	puts("gram_write: ");
-	uart_writeuint32(addr);
+	uart_writeuint32((unsigned long)addr);
 	puts(": ");
-	uart_writeuint32(value);
-	writel(value, addr);
+	uart_writeuint32((unsigned long)value);
+	writel(value, (unsigned long)addr);
 	puts("\n");
 
 	return 0;
@@ -88,14 +88,41 @@ int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
 
 int main(void) {
 	const int kNumIterations = 14;
-	int res, failcnt = 0, i=0;
+	int res, failcnt = 0;
 	uint32_t tmp;
+    unsigned long ftr, val;
 	volatile uint32_t *ram = (uint32_t*)DRAM_BASE;
 
 	console_init();
 	//puts("Firmware launched...\n");
 
-	puts("fw..");
+#if 1
+    puts(" Soc signature: ");
+    tmp = readl(SYSCON_BASE + SYS_REG_SIGNATURE);
+    uart_writeuint32(tmp);
+    puts("  Soc features: ");
+    ftr = readl(SYSCON_BASE + SYS_REG_INFO);
+    if (ftr & SYS_REG_INFO_HAS_UART)
+        puts("UART ");
+    if (ftr & SYS_REG_INFO_HAS_DRAM)
+        puts("DRAM ");
+    if (ftr & SYS_REG_INFO_HAS_BRAM)
+        puts("BRAM ");
+    if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
+        puts("SPIFLASH ");
+    if (ftr & SYS_REG_INFO_HAS_LITEETH)
+        puts("ETHERNET ");
+    puts("\r\n");
+
+    if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
+        puts("SPI Offset: ");
+        val = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
+        uart_writeuint32(val);
+        puts("\r\n");
+    }
+
+#endif
+
 #if 0
 #if 1
     // print out configuration parameters for QSPI
diff --git a/src/ls2.py b/src/ls2.py
index ce57269..7e75752 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -316,8 +316,10 @@ class DDR3SoC(SoC, Elaboratable):
             self._decoder.add(self.bootmem.bus, addr=fw_addr) # ROM at fw_addr
 
         # System Configuration info
+        spi_offset = spi0_addr if (spi_0_pins is not None) else None
         self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq,
-                                      has_uart=(uart_pins is not None))
+                                      has_uart=(uart_pins is not None),
+                                      spi_offset=spi_offset)
         self._decoder.add(self.syscon.bus, addr=0xc0000000) # at 0xc000_0000
 
         if False:
@@ -680,7 +682,7 @@ def build_platform(fpga, firmware):
 
     # Get SPI resource pins
     spi_0_pins = None
-    if False and platform is not None and \
+    if platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Override here to get FlashResource out of the way and enable Tercel
         # direct access to the SPI flash.
-- 
2.30.2