From c80315cea42414216bcc7b62acb2ef9a41b54eab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 5 Jan 2018 13:28:45 +0100 Subject: [PATCH] Bugfix in hierarchy handling of blackbox module ports Signed-off-by: Clifford Wolf --- frontends/ast/ast.cc | 2 +- frontends/ast/ast.h | 2 +- kernel/rtlil.cc | 4 +++- kernel/rtlil.h | 2 +- passes/hierarchy/hierarchy.cc | 9 ++++----- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index be04d5536..037a9f3ee 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1067,7 +1067,7 @@ AstModule::~AstModule() } // create a new parametric module (when needed) and return the name of the generated module -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict parameters) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict parameters, bool) { std::string stripped_name = name.str(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index a5d5ee30a..d1e2c78d1 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -283,7 +283,7 @@ namespace AST AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail); virtual RTLIL::Module *clone() const; }; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3e873054f..fb3d9dbe9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -639,8 +639,10 @@ RTLIL::Module::~Module() delete it->second; } -RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, bool mayfail) { + if (mayfail) + return RTLIL::IdString(); log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fc29e1e65..a251b4252 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -906,7 +906,7 @@ public: Module(); virtual ~Module(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); virtual void sort(); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 524d57854..c680dbbd8 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -625,16 +625,15 @@ struct HierarchyPass : public Pass { for (auto module : design->modules()) for (auto cell : module->cells()) { - if (GetSize(cell->parameters) != 0) - continue; - Module *m = design->module(cell->type); if (m == nullptr) continue; - if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) { - IdString new_m_name = m->derive(design, cell->parameters); + if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) { + IdString new_m_name = m->derive(design, cell->parameters, true); + if (new_m_name.empty()) + continue; if (new_m_name != m->name) { m = design->module(new_m_name); blackbox_derivatives.insert(m); -- 2.30.2