From c8042bf8f42f0676ba87171720cce12b14e1bd17 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 22 Jun 2022 19:08:20 +0100 Subject: [PATCH] --- openpower/sv/vector_ops/discussion.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/vector_ops/discussion.mdwn b/openpower/sv/vector_ops/discussion.mdwn index 2241840c2..f95d3c921 100644 --- a/openpower/sv/vector_ops/discussion.mdwn +++ b/openpower/sv/vector_ops/discussion.mdwn @@ -10,22 +10,24 @@ needs some work though def bmask(mode, RA, RB=None, zero=False): if _RB = 0 then mask <- [1] * XLEN else mask = (RB) a1 <- (RA) & mask - if mode[1] then a1 <- ~ra + if mode[1] then a1 <- ¬ra mode2 <- mode[2:3] if mode2 = 0 then a2 <- -ra if mode2 = 1 then a2 <- ra-1 if mode2 = 2 then a2 <- ra+1 - if mode2 = 3 then a2 <- ~(ra+1) + if mode2 = 3 then a2 <- ¬(ra+1) a1 <- a1 & mask a2 <- a2 & mask + # select operator mode3 <- mode[3:4] if mode3 = 0 then result <- a1 | a2 if mode3 = 1 then result <- a1 & a2 if mode3 = 2 then result <- a1 ^ a2 if mode3 = 3 then result <- UNDEFINED result <- result & mask + # optionally restore masked-out bits if L = 1 then - result <- result | (RA & ~mask) + result <- result | (RA & ¬mask) RT <- result SBF = 0b01010 # set before first -- 2.30.2