From c8074769b081f26b2129910502dd9031acd01a2a Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Mon, 11 Oct 2021 10:00:20 +0200 Subject: [PATCH] Add Verific adffe/dffsre/aldffe FIXMEs Signed-off-by: Claire Xenia Wolf --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 59fdda068..b8742e61d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1864,6 +1864,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Adffe if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); @@ -1875,6 +1876,7 @@ Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::Si log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Dffsre if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); @@ -1886,6 +1888,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL:: log_assert(gclk == false); log_assert(disable_sig == State::S0); + // FIXME: Aldffe if (enable_sig != State::S1) sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); -- 2.30.2