From c822619de1b2a07f2930545e4b0f187278ff3f13 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 13:20:03 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 1f31f6577..dbb528664 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -463,10 +463,7 @@ This contrivance is avoided by the behavioural inversion bits.
 
 # Pseudocode and examples
 
-For comparative purposes this is a copy of the v3.0B `bc` pseudocode,
-noting that M and AA have not been added to the SVP64 versions
-for simplicity of illustration.  ctr_ok does not appear in the SVP64
-versions because of the way that CTRtest Mode interacts.
+For comparative purposes this is a copy of the v3.0B `bc` pseudocode
 
 ```
 if (mode_is_64bit) then M <- 0
@@ -511,6 +508,8 @@ to the early-exit opportunities.
 Pseudocode for Horizontal-First Mode:
 
 ```
+if (mode_is_64bit) then M <- 0
+else M <- 32
 cond_ok = not SVRMmode.ALL
 for srcstep in range(VL):
     # select predicate bit or zero/one
@@ -524,11 +523,13 @@ for srcstep in range(VL):
       # inverted CTR test skip mode
       if ¬BO[2] & CTRtest & ¬CTI then
         CTR = CTR - 1
-        continue
+        continue # skip to next
     else
         testbit = SVRMmode.SNZ
+    if ¬BO[2] then CTR <- CTR - 1
+    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
     # actual element test here
-    el_cond_ok <- BO[0] | ¬(testbit ^ BO[1])
+    el_cond_ok <- BO[0] | ¬(testbit ^ BO[1]) & ctr_ok
     # merge in the test
     if SVRMmode.ALL:
         cond_ok &= el_cond_ok
@@ -542,12 +543,9 @@ for srcstep in range(VL):
             SVSTATE.VL = srcstep
         break
     # early exit?
-    if SVRMmode.ALL:
-        if ~el_cond_ok:
-            break
-    else
-        if el_cond_ok:
-            break
+    if SVRMmode.ALL != el_cond_ok:
+         break
+    # SVP64 rules about Scalar registers still apply!
     if SVCRf.scalar:
        break
 # loop finally done, now test if branch (and update LR)
@@ -557,7 +555,6 @@ if cond_ok then
     else       NIA <-iea CIA + EXTS(BD || 0b00)
     lr_ok <- 0b1
 if LK & lr_ok then LR <-iea CIA + 4
-
 ```
 
 Pseudocode for Vertical-First Mode:
-- 
2.30.2