From c83043ee58e86a1b1da7b76a2b2d34e1667923dc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 21 Aug 2020 16:37:10 +0100 Subject: [PATCH] get litex sim enabled with 32-bit wishbone bus --- src/soc/litex/florent/libresoc/core.py | 11 ++++++++--- src/soc/litex/florent/sim.py | 12 +++++++++++- src/soc/minerva/units/loadstore.py | 13 ++++++++----- src/soc/simple/issuer.py | 2 +- src/soc/simple/issuer_verilog.py | 2 ++ src/soc/simple/test/test_issuer.py | 1 + 6 files changed, 31 insertions(+), 10 deletions(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 49e4bd3a..f0852aeb 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -5,14 +5,13 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU -CPU_VARIANTS = ["standard"] +CPU_VARIANTS = ["standard", "standard32"] class LibreSoC(CPU): name = "libre_soc" human_name = "Libre-SoC" variants = CPU_VARIANTS - data_width = 64 endianness = "little" gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu") linker_output_format = "elf64-powerpcle" @@ -44,8 +43,14 @@ class LibreSoC(CPU): self.variant = variant self.reset = Signal() + + if variant == "standard32": + self.data_width = 32 + self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30) + else: + self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29) + self.data_width = 64 self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29) - self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29) self.periph_buses = [ibus, dbus] self.memory_buses = [] diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index d451e614..e2d516bb 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -37,12 +37,21 @@ class LibreSoCSim(SoCSDRAM): platform = Platform() sys_clk_freq = int(100e6) + cpu_data_width = 32 + #cpu_data_width = 64 + + if cpu_data_width == 32: + variant = "standard32" + else: + variant = "standard" + # SoCCore ------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type = "microwatt", cpu_cls = LibreSoC if cpu == "libresoc" \ else Microwatt, #bus_data_width = 64, + cpu_variant = variant, csr_data_width = 32, l2_cache_size = 0, uart_name = "sim", @@ -201,8 +210,9 @@ class LibreSoCSim(SoCSDRAM): ) # limit range of pc for debug reporting - self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234)) + #self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234)) #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58)) + self.comb += active_dbg.eq(1) # get the MSR self.sync += If(active_dbg & (uptime[0:cyclewid] == 28), diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index 3241e20e..7476380d 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -16,19 +16,22 @@ class LoadStoreUnitInterface: def __init__(self, pspec): self.pspec = pspec self.pspecslave = pspec - self.dbus = self.slavebus = Record(make_wb_layout(pspec)) - print(self.dbus.sel.shape()) - self.needs_cvt = False if (hasattr(pspec, "dmem_test_depth") and isinstance(pspec.wb_data_wid, int) and pspec.wb_data_wid != pspec.reg_wid): + self.dbus = Record(make_wb_layout(pspec), name="int_dbus") pspecslave = deepcopy(pspec) pspecslave.reg_wid = pspec.wb_data_wid mask_ratio = (pspec.reg_wid // pspec.wb_data_wid) pspecslave.mask_wid = pspec.mask_wid // mask_ratio self.pspecslave = pspecslave - self.slavebus = Record(make_wb_layout(pspecslave)) + self.slavebus = Record(make_wb_layout(pspecslave), name="dbus") self.needs_cvt = True + else: + self.needs_cvt = False + self.dbus = self.slavebus = Record(make_wb_layout(pspec)) + + print(self.dbus.sel.shape()) self.mask_wid = mask_wid = pspec.mask_wid self.addr_wid = addr_wid = pspec.addr_wid self.data_wid = data_wid = pspec.reg_wid @@ -83,7 +86,7 @@ class LoadStoreUnitInterface: yield self.m_load_err_o yield self.m_store_err_o yield self.m_badaddr_o - for sig in self.dbus.fields.values(): + for sig in self.slavebus.fields.values(): yield sig def ports(self): diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index edcb18bc..ad4fd0a9 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -283,7 +283,7 @@ class TestIssuer(Elaboratable): ] + \ list(self.dbg.dmi.ports()) + \ list(self.imem.ibus.fields.values()) + \ - list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values()) + list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values()) def ports(self): return list(self) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 9ba52fe6..f8f52d76 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -25,6 +25,8 @@ if __name__ == '__main__': reg_wid=64, # set to 32 for instruction-memory width=32 imem_reg_wid=64, + # set to 32 to make data wishbone bus 32-bit + wb_data_wid=32, units=units) dut = TestIssuer(pspec) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index ebe81021..b461c731 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -142,6 +142,7 @@ class TestRunner(FHDLTestCase): addr_wid=48, mask_wid=8, imem_reg_wid=64, + #wb_data_width=32, reg_wid=64) m.submodules.issuer = issuer = TestIssuer(pspec) imem = issuer.imem._get_memory() -- 2.30.2