From c83a66755553f47f40c591110e6bdcd722360d6c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:08:46 -0700 Subject: [PATCH] Fix width of D --- passes/pmgen/xilinx_dsp.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 3cfaa9371..adc09a6e4 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -48,7 +48,7 @@ static Cell* addDsp(Module *module) { cell->setParam(ID(USE_SIMD), Const("ONE48")); cell->setParam(ID(USE_DPORT), Const("FALSE")); - cell->setPort(ID(D), Const(0, 24)); + cell->setPort(ID(D), Const(0, 25)); cell->setPort(ID(INMODE), Const(0, 5)); cell->setPort(ID(ALUMODE), Const(0, 4)); cell->setPort(ID(OPMODE), Const(0, 7)); -- 2.30.2