From c8405281a372fb473744d27251356ca53ab5a2d6 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 7 Aug 2023 16:04:00 -0700 Subject: [PATCH] split out instructions from openpower/isa/branch.mdwn --- openpower/isa/branch.mdwn | 109 ++------------------------- openpower/isa/branch/b.mdwn | 16 ++++ openpower/isa/branch/b_code.mdwn | 3 + openpower/isa/branch/bc.mdwn | 17 +++++ openpower/isa/branch/bc_code.mdwn | 9 +++ openpower/isa/branch/bcctr.mdwn | 14 ++++ openpower/isa/branch/bcctr_code.mdwn | 3 + openpower/isa/branch/bclr.mdwn | 15 ++++ openpower/isa/branch/bclr_code.mdwn | 7 ++ openpower/isa/branch/bctar.mdwn | 18 +++++ openpower/isa/branch/bctar_code.mdwn | 7 ++ 11 files changed, 114 insertions(+), 104 deletions(-) create mode 100644 openpower/isa/branch/b.mdwn create mode 100644 openpower/isa/branch/b_code.mdwn create mode 100644 openpower/isa/branch/bc.mdwn create mode 100644 openpower/isa/branch/bc_code.mdwn create mode 100644 openpower/isa/branch/bcctr.mdwn create mode 100644 openpower/isa/branch/bcctr_code.mdwn create mode 100644 openpower/isa/branch/bclr.mdwn create mode 100644 openpower/isa/branch/bclr_code.mdwn create mode 100644 openpower/isa/branch/bctar.mdwn create mode 100644 openpower/isa/branch/bctar_code.mdwn diff --git a/openpower/isa/branch.mdwn b/openpower/isa/branch.mdwn index 5867ea87..dd2b56d2 100644 --- a/openpower/isa/branch.mdwn +++ b/openpower/isa/branch.mdwn @@ -20,111 +20,12 @@ -# Branch +[[!inline pagenames="openpower/isa/branch/b" raw="yes"]] -I-Form +[[!inline pagenames="openpower/isa/branch/bc" raw="yes"]] -* b target_addr (AA=0 LK=0) -* ba target_addr (AA=1 LK=0) -* bl target_addr (AA=0 LK=1) -* bla target_addr (AA=1 LK=1) +[[!inline pagenames="openpower/isa/branch/bclr" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/branch/bcctr" raw="yes"]] - if AA then NIA <-iea EXTS(LI || 0b00) - else NIA <-iea CIA + EXTS(LI || 0b00) - if LK then LR <-iea CIA + 4 - -Special Registers Altered: - - LR (if LK=1) - -# Branch Conditional - -B-Form - -* bc BO,BI,target_addr (AA=0 LK=0) -* bca BO,BI,target_addr (AA=1 LK=0) -* bcl BO,BI,target_addr (AA=0 LK=1) -* bcla BO,BI,target_addr (AA=1 LK=1) - -Pseudo-code: - - if (mode_is_64bit) then M <- 0 - else M <- 32 - if ¬BO[2] then CTR <- CTR - 1 - ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) - cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) - if ctr_ok & cond_ok then - if AA then NIA <-iea EXTS(BD || 0b00) - else NIA <-iea CIA + EXTS(BD || 0b00) - if LK then LR <-iea CIA + 4 - -Special Registers Altered: - - CTR (if BO2=0) - LR (if LK=1) - -# Branch Conditional to Link Register - -XL-Form - -* bclr BO,BI,BH (LK=0) -* bclrl BO,BI,BH (LK=1) - -Pseudo-code: - - if (mode_is_64bit) then M <- 0 - else M <- 32 - if ¬BO[2] then CTR <- CTR - 1 - ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) - cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) - if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00 - if LK then LR <-iea CIA + 4 - -Special Registers Altered: - - CTR (if BO2=0) - LR (if LK=1) - -# Branch Conditional to Count Register - -XL-Form - -* bcctr BO,BI,BH (LK=0) -* bcctrl BO,BI,BH (LK=1) - -Pseudo-code: - - cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) - if cond_ok then NIA <-iea CTR[0:61] || 0b00 - if LK then LR <-iea CIA + 4 - -Special Registers Altered: - - LR (if LK=1) - -# Branch Conditional to Branch Target Address Register - -XL-Form - -* bctar BO,BI,BH (LK=0) -* bctarl BO,BI,BH (LK=1) - -Pseudo-code: - - if (mode_is_64bit) then M <- 0 - else M <- 32 - if ¬BO[2] then CTR <- CTR - 1 - ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) - cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) - if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00 - if LK then LR <-iea CIA + 4 - -Special Registers Altered: - - CTR (if BO2=0) - LR (if LK=1) - - - +[[!inline pagenames="openpower/isa/branch/bctar" raw="yes"]] diff --git a/openpower/isa/branch/b.mdwn b/openpower/isa/branch/b.mdwn new file mode 100644 index 00000000..ca7efdaf --- /dev/null +++ b/openpower/isa/branch/b.mdwn @@ -0,0 +1,16 @@ +# Branch + +I-Form + +* b target_addr (AA=0 LK=0) +* ba target_addr (AA=1 LK=0) +* bl target_addr (AA=0 LK=1) +* bla target_addr (AA=1 LK=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/branch/b_code" raw="yes"]] + +Special Registers Altered: + + LR (if LK=1) diff --git a/openpower/isa/branch/b_code.mdwn b/openpower/isa/branch/b_code.mdwn new file mode 100644 index 00000000..0491ce5e --- /dev/null +++ b/openpower/isa/branch/b_code.mdwn @@ -0,0 +1,3 @@ + if AA then NIA <-iea EXTS(LI || 0b00) + else NIA <-iea CIA + EXTS(LI || 0b00) + if LK then LR <-iea CIA + 4 diff --git a/openpower/isa/branch/bc.mdwn b/openpower/isa/branch/bc.mdwn new file mode 100644 index 00000000..ed0c842e --- /dev/null +++ b/openpower/isa/branch/bc.mdwn @@ -0,0 +1,17 @@ +# Branch Conditional + +B-Form + +* bc BO,BI,target_addr (AA=0 LK=0) +* bca BO,BI,target_addr (AA=1 LK=0) +* bcl BO,BI,target_addr (AA=0 LK=1) +* bcla BO,BI,target_addr (AA=1 LK=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/branch/bc_code" raw="yes"]] + +Special Registers Altered: + + CTR (if BO2=0) + LR (if LK=1) diff --git a/openpower/isa/branch/bc_code.mdwn b/openpower/isa/branch/bc_code.mdwn new file mode 100644 index 00000000..dfc9b6a2 --- /dev/null +++ b/openpower/isa/branch/bc_code.mdwn @@ -0,0 +1,9 @@ + if (mode_is_64bit) then M <- 0 + else M <- 32 + if ¬BO[2] then CTR <- CTR - 1 + ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) + cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) + if ctr_ok & cond_ok then + if AA then NIA <-iea EXTS(BD || 0b00) + else NIA <-iea CIA + EXTS(BD || 0b00) + if LK then LR <-iea CIA + 4 diff --git a/openpower/isa/branch/bcctr.mdwn b/openpower/isa/branch/bcctr.mdwn new file mode 100644 index 00000000..4addc1c1 --- /dev/null +++ b/openpower/isa/branch/bcctr.mdwn @@ -0,0 +1,14 @@ +# Branch Conditional to Count Register + +XL-Form + +* bcctr BO,BI,BH (LK=0) +* bcctrl BO,BI,BH (LK=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/branch/bcctr_code" raw="yes"]] + +Special Registers Altered: + + LR (if LK=1) diff --git a/openpower/isa/branch/bcctr_code.mdwn b/openpower/isa/branch/bcctr_code.mdwn new file mode 100644 index 00000000..d6a8c817 --- /dev/null +++ b/openpower/isa/branch/bcctr_code.mdwn @@ -0,0 +1,3 @@ + cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) + if cond_ok then NIA <-iea CTR[0:61] || 0b00 + if LK then LR <-iea CIA + 4 diff --git a/openpower/isa/branch/bclr.mdwn b/openpower/isa/branch/bclr.mdwn new file mode 100644 index 00000000..2670013a --- /dev/null +++ b/openpower/isa/branch/bclr.mdwn @@ -0,0 +1,15 @@ +# Branch Conditional to Link Register + +XL-Form + +* bclr BO,BI,BH (LK=0) +* bclrl BO,BI,BH (LK=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/branch/bclr_code" raw="yes"]] + +Special Registers Altered: + + CTR (if BO2=0) + LR (if LK=1) diff --git a/openpower/isa/branch/bclr_code.mdwn b/openpower/isa/branch/bclr_code.mdwn new file mode 100644 index 00000000..ea8a5aa9 --- /dev/null +++ b/openpower/isa/branch/bclr_code.mdwn @@ -0,0 +1,7 @@ + if (mode_is_64bit) then M <- 0 + else M <- 32 + if ¬BO[2] then CTR <- CTR - 1 + ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) + cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) + if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00 + if LK then LR <-iea CIA + 4 diff --git a/openpower/isa/branch/bctar.mdwn b/openpower/isa/branch/bctar.mdwn new file mode 100644 index 00000000..7cabee20 --- /dev/null +++ b/openpower/isa/branch/bctar.mdwn @@ -0,0 +1,18 @@ +# Branch Conditional to Branch Target Address Register + +XL-Form + +* bctar BO,BI,BH (LK=0) +* bctarl BO,BI,BH (LK=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/branch/bctar_code" raw="yes"]] + +Special Registers Altered: + + CTR (if BO2=0) + LR (if LK=1) + + + diff --git a/openpower/isa/branch/bctar_code.mdwn b/openpower/isa/branch/bctar_code.mdwn new file mode 100644 index 00000000..04319a7b --- /dev/null +++ b/openpower/isa/branch/bctar_code.mdwn @@ -0,0 +1,7 @@ + if (mode_is_64bit) then M <- 0 + else M <- 32 + if ¬BO[2] then CTR <- CTR - 1 + ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) + cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) + if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00 + if LK then LR <-iea CIA + 4 -- 2.30.2