From c85382a022e0665c08d9e2d6f4fc29be39437afe Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 14 Dec 2018 05:17:43 +0000 Subject: [PATCH] back.pysim: delay clock processes by one half period. Makes it easier to see initial delta cycles. --- nmigen/back/pysim.py | 1 + 1 file changed, 1 insertion(+) diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 3975443..478a738 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -231,6 +231,7 @@ class Simulator: half_period = period / 2 def clk_process(): yield Passive() + yield Delay(half_period) while True: yield clk.eq(1) yield Delay(half_period) -- 2.30.2