From c88f971a7de1e8f6c0d5e8f56b1b0d44b3a92b3f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 11:36:34 +0100 Subject: [PATCH] add reconfigureable Load/Store class --- src/soc/config/loadstore.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 src/soc/config/loadstore.py diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py new file mode 100644 index 00000000..8291276a --- /dev/null +++ b/src/soc/config/loadstore.py @@ -0,0 +1,20 @@ +"""ConfigureableLoadStoreUnit + +allows the type of LoadStoreUnit to be run-time selectable + +""" +from soc.experiment.pimem import TestMemoryLoadStoreUnit +from soc.minerva.units.loadstore import BareLoadStoreUnit, CacheLoadStoreUnit + + +class ConfigureableLoadStoreUnit: + def __init__(self, pspec): + lsidict = {'testmem': TestMemoryLoadStoreUnit, + 'bare_wb': BareLoadStoreUnit, + 'cache_wb': CacheLoadStoreUnit # TODO dcache parameters + } + lsikls = lsidict[pspec.ldst_ifacetype] + self.lsi = lsikls(addr_wid=pspec.addr_wid, + mask_wid=pspec.mask_wid, # cache line range + data_wid=pspec.reg_wid) + -- 2.30.2