From c89f618a57b299169e1bcbe4a342278247ad2ce5 Mon Sep 17 00:00:00 2001 From: Sadoon Albader Date: Fri, 8 Dec 2023 20:48:59 +0300 Subject: [PATCH] proper svp64 implementation of first part of blocks --- crypto/poly1305/poly1305-donna-test.py | 49 +++++++++++++++++--------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/crypto/poly1305/poly1305-donna-test.py b/crypto/poly1305/poly1305-donna-test.py index 75d9c022..999d9a04 100644 --- a/crypto/poly1305/poly1305-donna-test.py +++ b/crypto/poly1305/poly1305-donna-test.py @@ -208,28 +208,43 @@ class Poly1305Donna(object): t0 = self.le_bytes_to_num(m[0:8]) t1 = self.le_bytes_to_num(m[8:16]) - #h0 += simulation(["and. 0, 1, 2"], h0, t0, 0xfffffffffff) - # h0 = h0 + t0 & 0xfff... - novar = 0xdeadbeef - h0_sim = simulation(["and. 10, 1, 2","add 0, 0, 10"], h0, t0, 0xfffffffffff) - t0_temp = simulation(["srd 0, 1, 2"], novar, t0, 44) - t1_temp = simulation(["sld 0, 1, 2"], novar, t1, 20) - h1_sim = simulation(["and. 10, 1, 2","add 0, 0, 10"], - h1, - simulation(["or. 0, 1, 2"], novar, t0_temp, t1_temp), - 0xfffffffffff) - t1_temp = simulation(["srd 0, 1, 2"], novar, t1, 24) - t1_temp = simulation(["and. 0, 1, 2"], novar, t1_temp, 0x3ffffffffff) - t1_temp = simulation(["or. 0, 1, 2"], novar, t1_temp, hibit ) - h2_sim = simulation(["add 0, 1, 2"], novar, h2, t1_temp) + initial_regs = [0] * 32 + initial_regs[0] = 0xfffffffffff + initial_regs[1] = 0xfffffffffff + initial_regs[2] = 0x3ffffffffff + initial_regs[3] = h0 + initial_regs[4] = h1 + initial_regs[5] = h2 + initial_regs[6] = 44 + initial_regs[7] = 20 + initial_regs[8] = 24 + initial_regs[9] = t0 + initial_regs[10]= t1 + initial_regs[30]= hibit + + # could use remap here as Luke suggested + # bug #1157c3 https://bugs.libre-soc.org/show_bug.cgi?id=1157#c3 + lst = SVP64Asm([ + 'or 11, 9, 9', # move t0 to r11 + 'rldicl 20, 9, %d, 44' %(64-44), # equivelant to srdi + 'rldicr 21, 10, 20, %d' %(63-20), # equivelant to sldi + 'or 12, 20, 21', # move result to r12, 20&21 are temps + 'rldicl 13, 10, %d, 24' %(64-24), + 'or 13, 13, 30', # to accommodate hibit + 'setvl 0, 0, 3, 0, 1, 1', + 'sv.and *11, *11, *0', + 'sv.add *3, *3, *11', + ]) + lst = list(lst) + final_regs = simulation_svp(lst, initial_regs) h0 += t0 & 0xfffffffffff; h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff); h2 += (((t1 >> 24) ) & 0x3ffffffffff) | hibit; - assert (h0 == h0_sim), "h0 and h0_sim are unequal!" - assert (h1 == h1_sim), "h1 and h1_sim are uneqaul!" - assert (h2 == h2_sim), "h2 and h2_sim are unequal!" + assert (h0 == final_regs[3].value), "h0 and h0_sim are unequal!" + assert (h1 == final_regs[4].value), "h1 and h1_sim are uneqaul!" + assert (h2 == final_regs[5].value), "h2 and h2_sim are unequal!" print(" loop h+t %x %x %x" % (h0, h1, h2)) -- 2.30.2