From c8a102c6afcdf0c71b3706f81030195e57f84203 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 2 Feb 2020 15:27:41 -0800 Subject: [PATCH] arm: Use static_cast to get access the ARM specific ISA functions. Change-Id: I8d237fa60c0fc17c97ed351afd0fa3c623262f0d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25006 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/insts/misc64.cc | 14 ++++++++++---- src/arch/arm/insts/static_inst.cc | 3 ++- src/arch/arm/miscregs.cc | 3 ++- src/arch/arm/utility.cc | 14 ++++++++++---- 4 files changed, 24 insertions(+), 10 deletions(-) diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 0c263fb65..9bb4026c4 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -269,13 +269,19 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, break; // GICv3 regs case MISCREG_ICC_SGI0R_EL1: - if (tc->getIsaPtr()->haveGICv3CpuIfc()) - trap_to_hyp = hcr.fmo && el == EL1; + { + auto *isa = static_cast(tc->getIsaPtr()); + if (isa->haveGICv3CpuIfc()) + trap_to_hyp = hcr.fmo && el == EL1; + } break; case MISCREG_ICC_SGI1R_EL1: case MISCREG_ICC_ASGI1R_EL1: - if (tc->getIsaPtr()->haveGICv3CpuIfc()) - trap_to_hyp = hcr.imo && el == EL1; + { + auto *isa = static_cast(tc->getIsaPtr()); + if (isa->haveGICv3CpuIfc()) + trap_to_hyp = hcr.imo && el == EL1; + } break; default: break; diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 1f849b971..644cafd85 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1166,7 +1166,8 @@ ArmStaticInst::generalExceptionsToAArch64(ThreadContext *tc, unsigned ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc) { - return tc->getIsaPtr()->getCurSveVecLenInBits(tc); + auto *isa = static_cast(tc->getIsaPtr()); + return isa->getCurSveVecLenInBits(tc); } } diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 87e130c2b..4785f00cd 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1080,8 +1080,9 @@ snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc) { + auto *isa = static_cast(tc->getIsaPtr()); SCR scr = tc->readMiscReg(MISCREG_SCR); - return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns); + return isa->snsBankedIndex64(reg, scr.ns); } /** diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index e8ca13d0e..44bc7372e 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -612,13 +612,19 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss) break; // GICv3 regs case MISCREG_ICC_SGI0R: - if (tc->getIsaPtr()->haveGICv3CpuIfc()) - trapToHype = hcr.fmo; + { + auto *isa = static_cast(tc->getIsaPtr()); + if (isa->haveGICv3CpuIfc()) + trapToHype = hcr.fmo; + } break; case MISCREG_ICC_SGI1R: case MISCREG_ICC_ASGI1R: - if (tc->getIsaPtr()->haveGICv3CpuIfc()) - trapToHype = hcr.imo; + { + auto *isa = static_cast(tc->getIsaPtr()); + if (isa->haveGICv3CpuIfc()) + trapToHype = hcr.imo; + } break; // No default action needed default: -- 2.30.2