From c8bcbfb855cf48b493b15f465f0f38890c692bdd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 15:51:17 +0200 Subject: [PATCH] litesata: pep8 (E261, E271) --- misoclib/mem/litesata/common.py | 2 +- misoclib/mem/litesata/core/link/scrambler.py | 4 ++-- misoclib/mem/litesata/example_designs/targets/bist.py | 2 +- misoclib/mem/litesata/example_designs/test/bist.py | 2 +- misoclib/mem/litesata/frontend/bist.py | 2 +- misoclib/mem/litesata/phy/ctrl.py | 4 ++-- misoclib/mem/litesata/phy/k7/trx.py | 2 +- misoclib/mem/litesata/test/hdd.py | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py index 6c28da74..92e59ca3 100644 --- a/misoclib/mem/litesata/common.py +++ b/misoclib/mem/litesata/common.py @@ -254,7 +254,7 @@ def command_rx_data_description(dw): return EndpointDescription(layout, packetized=True) # HDD -logical_sector_size = 512 # constant since all HDDs use this +logical_sector_size = 512 # constant since all HDDs use this def dwords2sectors(n): diff --git a/misoclib/mem/litesata/core/link/scrambler.py b/misoclib/mem/litesata/core/link/scrambler.py index 45b01949..948c5379 100644 --- a/misoclib/mem/litesata/core/link/scrambler.py +++ b/misoclib/mem/litesata/core/link/scrambler.py @@ -24,7 +24,7 @@ class Scrambler(Module): # XXX: from SATA specification, replace it with # a generic implementation using polynoms. lfsr_coefs = ( - (15, 13, 4, 0), #0 + (15, 13, 4, 0), # 0 (15, 14, 13, 5, 4, 1, 0), (14, 13, 6, 5, 4, 2, 1, 0), (15, 14, 7, 6, 5, 3, 2, 1), @@ -41,7 +41,7 @@ class Scrambler(Module): (15, 13, 12, 11, 9, 5, 3, 2), (15, 14, 12, 10, 6, 3, 0), - (11, 7, 1, 0), #16 + (11, 7, 1, 0), # 16 (12, 8, 2, 1), (13, 9, 3, 2), (14, 10, 4, 3), diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index 806019b6..e52e8547 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -105,7 +105,7 @@ class BISTSoC(SoC, AutoCSR): # SATA PHY/Core/Frontend self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq) - self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME + self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True) # Status Leds diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py index 40cf5177..019e736a 100644 --- a/misoclib/mem/litesata/example_designs/test/bist.py +++ b/misoclib/mem/litesata/example_designs/test/bist.py @@ -86,7 +86,7 @@ class LiteSATABISTIdentifyDriver: self.source_ack.write(1) def run(self, blocking=True): - self.read_fifo() # flush the fifo before we start + self.read_fifo() # flush the fifo before we start self.start.write(1) if blocking: while (self.done.read() == 0): diff --git a/misoclib/mem/litesata/frontend/bist.py b/misoclib/mem/litesata/frontend/bist.py index fe675fbf..6924a1bb 100644 --- a/misoclib/mem/litesata/frontend/bist.py +++ b/misoclib/mem/litesata/frontend/bist.py @@ -13,7 +13,7 @@ class LiteSATABISTGenerator(Module): self.done = Signal() self.aborted = Signal() - self.errors = Signal(32) # Note: Not used for writes + self.errors = Signal(32) # Note: Not used for writes ### diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py index 63ebbf7c..71906700 100644 --- a/misoclib/mem/litesata/phy/ctrl.py +++ b/misoclib/mem/litesata/phy/ctrl.py @@ -91,7 +91,7 @@ class LiteSATAPHYCtrl(Module): ) fsm.act("AWAIT_NO_RX_IDLE", trx.tx_idle.eq(0), - source.data.eq(0x4A4A4A4A), #D10.2 + source.data.eq(0x4A4A4A4A), # D10.2 source.charisk.eq(0b0000), If(~trx.rx_idle, NextState("AWAIT_ALIGN"), @@ -101,7 +101,7 @@ class LiteSATAPHYCtrl(Module): ) fsm.act("AWAIT_ALIGN", trx.tx_idle.eq(0), - source.data.eq(0x4A4A4A4A), #D10.2 + source.data.eq(0x4A4A4A4A), # D10.2 source.charisk.eq(0b0000), trx.rx_align.eq(1), align_timeout.ce.eq(1), diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py index 72da64bf..deae5d1b 100644 --- a/misoclib/mem/litesata/phy/k7/trx.py +++ b/misoclib/mem/litesata/phy/k7/trx.py @@ -815,7 +815,7 @@ class K7LiteSATAPHYTRX(Module): o_TXOUTCLK=self.txoutclk, #o_TXOUTCLKFABRIC=, #o_TXOUTCLKPCS=, - i_TXOUTCLKSEL=0b11, #?? + i_TXOUTCLKSEL=0b11, # ?? #o_TXRATEDONE=, # Transmit Ports - TX Gearbox Ports i_TXCHARISK=self.txcharisk, diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index c1b9c3d4..e75bbff0 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -152,7 +152,7 @@ class LinkTXPacket(LinkPacket): class LinkLayer(Module): - def __init__(self, phy, debug=False, random_level=0): + def __init__(self, phy, debug=False, random_level=0): self.phy = phy self.debug = debug self.random_level = random_level -- 2.30.2