From c8bfba7a93ec76d9bd36f15003430437e778fe7b Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 3 Apr 2022 16:08:44 +0100
Subject: [PATCH]

---
 openpower/sv/normal.mdwn | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index afb375d0c..16f8d4c0d 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -114,8 +114,9 @@ dest elwidth.
 Reduction in SVP64 is similar in essence to other Vector Processing
 ISAs, but leverages the underlying scalar Base v3.0B operations.
 Thus it is more a convention that the programmer may utilise to give
-the appearance and effect of a Horizontal Vector Reduction.
-Details are in the [[svp64/appendix]]
+the appearance and effect of a Horizontal Vector Reduction. Due
+to the unusual decoupling it is also possible to perform
+prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]
 
 # Fail-on-first
 
-- 
2.30.2