From c8c38bc3b07eed36a450dd6763d87531d198d8b2 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Nov 2018 02:24:41 +0000
Subject: [PATCH] add pyrtl pipeline introspection example

---
 3d_gpu/microarchitecture.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 4cab848e0..de5fc3346 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -111,3 +111,4 @@ called the flip-flops orchestrating the timing "collectors".
 * <https://en.wikipedia.org/wiki/Reservation_station>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
+* <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>
-- 
2.30.2