From c8c9c4868429f98e77f782637568e9eed2dd33f9 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 26 Aug 2019 15:21:40 -0700 Subject: [PATCH] intel/compiler: Fix src0/desc setter ordering src0 vstride and type overlap with bits of the extended descriptor. brw_set_desc() also sets the extended descriptor to 0. So by setting the descriptor, then setting src0, we were accidentally setting a bunch of extended descriptor bits unintentionally. When using this infrastructure for framebuffer writes (in a future patch), this ended up setting the extended descriptor bit 20, which is "Null Render Target" on Icelake, causing nothing to be written to the framebuffer. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_eu_emit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 60761e83c62..1fb5156937c 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2525,8 +2525,8 @@ brw_send_indirect_message(struct brw_codegen *p, if (desc.file == BRW_IMMEDIATE_VALUE) { send = next_insn(p, BRW_OPCODE_SEND); + brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_set_desc(p, send, desc.ud | desc_imm); - } else { struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); @@ -2545,11 +2545,11 @@ brw_send_indirect_message(struct brw_codegen *p, brw_pop_insn_state(p); send = next_insn(p, BRW_OPCODE_SEND); + brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_set_src1(p, send, addr); } brw_set_dest(p, send, dst); - brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_inst_set_sfid(devinfo, send, sfid); brw_inst_set_eot(devinfo, send, eot); } -- 2.30.2