From c8d94f1d538860d80606701d15beecb308bbbcc2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Apr 2021 16:28:28 +0100 Subject: [PATCH] remove unneeded imports in sim test cases --- src/openpower/simulator/test_div_sim.py | 34 +++++++------------ .../simulator/test_helloworld_sim.py | 12 +------ src/openpower/simulator/test_mul_sim.py | 12 +------ src/openpower/simulator/test_shift_sim.py | 11 +----- src/openpower/simulator/test_sim.py | 11 ++---- src/openpower/simulator/test_trap_sim.py | 10 ------ 6 files changed, 19 insertions(+), 71 deletions(-) diff --git a/src/openpower/simulator/test_div_sim.py b/src/openpower/simulator/test_div_sim.py index 394c1a96..0cad521b 100644 --- a/src/openpower/simulator/test_div_sim.py +++ b/src/openpower/simulator/test_div_sim.py @@ -1,19 +1,11 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, SPR, - get_signal_name, get_csv) -from openpower.decoder.power_decoder2 import (PowerDecode2) +from nmutil.formaltest import FHDLTestCase from openpower.simulator.program import Program from openpower.simulator.qemu import run_program from openpower.decoder.isa.all import ISA from openpower.test.common import TestCase from openpower.simulator.test_sim import DecoderBase +from openpower.endian import bigendian @@ -29,7 +21,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "divw 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_1_divw_(self): @@ -37,7 +29,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "divw. 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_2_divw_(self): @@ -45,7 +37,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x5678", "divw. 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_1_divwe(self): @@ -53,7 +45,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "divwe 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_2_divweu(self): @@ -61,7 +53,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "divweu 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_4_moduw(self): @@ -69,7 +61,7 @@ class DivTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "moduw 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_5_div_regression(self): @@ -79,7 +71,7 @@ class DivTestCases(FHDLTestCase): "neg 1, 1", "divwo 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, @@ -102,7 +94,7 @@ class DivZeroTestCases(FHDLTestCase): "addi 2, 0, 0x0", "divw 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_1_divwe(self): @@ -110,7 +102,7 @@ class DivZeroTestCases(FHDLTestCase): "addi 2, 0, 0x0", "divwe 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_2_divweu(self): @@ -118,7 +110,7 @@ class DivZeroTestCases(FHDLTestCase): "addi 2, 0, 0x0", "divweu 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def test_4_moduw(self): @@ -126,7 +118,7 @@ class DivZeroTestCases(FHDLTestCase): "addi 2, 0, 0x0", "moduw 3, 1, 2", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, diff --git a/src/openpower/simulator/test_helloworld_sim.py b/src/openpower/simulator/test_helloworld_sim.py index 85cfe4aa..03d1e4a4 100644 --- a/src/openpower/simulator/test_helloworld_sim.py +++ b/src/openpower/simulator/test_helloworld_sim.py @@ -1,17 +1,7 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, SPR, - get_signal_name, get_csv) -from openpower.decoder.power_decoder2 import (PowerDecode2) +from nmutil.formaltest import FHDLTestCase from openpower.simulator.program import Program from openpower.simulator.qemu import run_program -from openpower.decoder.isa.all import ISA from openpower.test.common import TestCase from openpower.simulator.test_sim import DecoderBase from openpower.endian import bigendian diff --git a/src/openpower/simulator/test_mul_sim.py b/src/openpower/simulator/test_mul_sim.py index 52dc23f2..df1692ff 100644 --- a/src/openpower/simulator/test_mul_sim.py +++ b/src/openpower/simulator/test_mul_sim.py @@ -1,17 +1,7 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, SPRfull, - get_signal_name, get_csv) -from openpower.decoder.power_decoder2 import (PowerDecode2) +from nmutil.formaltest import FHDLTestCase from openpower.simulator.program import Program from openpower.simulator.qemu import run_program -from openpower.decoder.isa.all import ISA from openpower.test.common import TestCase from openpower.simulator.test_sim import DecoderBase from openpower.endian import bigendian diff --git a/src/openpower/simulator/test_shift_sim.py b/src/openpower/simulator/test_shift_sim.py index bed9bf45..47e93665 100644 --- a/src/openpower/simulator/test_shift_sim.py +++ b/src/openpower/simulator/test_shift_sim.py @@ -1,14 +1,5 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, SPR, - get_signal_name, get_csv) -from openpower.decoder.power_decoder2 import (PowerDecode2) +from nmutil.formaltest import FHDLTestCase from openpower.simulator.program import Program from openpower.simulator.qemu import run_program from openpower.decoder.isa.all import ISA diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py index a18b8bce..8c020819 100644 --- a/src/openpower/simulator/test_sim.py +++ b/src/openpower/simulator/test_sim.py @@ -1,13 +1,8 @@ -from nmigen import Module, Signal +import unittest +from nmigen import Module from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase -import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, - get_signal_name, get_csv) +from openpower.decoder.power_decoder import create_pdecode from openpower.decoder.power_decoder2 import (PowerDecode2) from openpower.simulator.program import Program from openpower.simulator.qemu import run_program diff --git a/src/openpower/simulator/test_trap_sim.py b/src/openpower/simulator/test_trap_sim.py index b6c95803..e8f08b3b 100644 --- a/src/openpower/simulator/test_trap_sim.py +++ b/src/openpower/simulator/test_trap_sim.py @@ -1,17 +1,7 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_enums import (Function, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, - single_bit_flags, Form, SPR, - get_signal_name, get_csv) -from openpower.decoder.power_decoder2 import (PowerDecode2) from openpower.simulator.program import Program from openpower.simulator.qemu import run_program -from openpower.decoder.isa.all import ISA from openpower.test.common import TestCase from openpower.simulator.test_sim import DecoderBase from openpower.endian import bigendian #XXX HACK! -- 2.30.2