From c8e9e6c73e1c5004485220605c90c3fe8dc4f0d4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Jun 2020 22:41:18 +0100 Subject: [PATCH] add cached fetch unit pass-through args --- src/soc/minerva/units/fetch.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index 6b78e801..023f8909 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -75,13 +75,13 @@ class BareFetchUnit(FetchUnitInterface, Elaboratable): class CachedFetchUnit(FetchUnitInterface, Elaboratable): - def __init__(self, *icache_args): - super().__init__() + def __init__(self, *icache_args, addr_wid=32, data_wid=32): + super().__init__(addr_wid=addr_wid, data_wid=data_wid) self.icache_args = icache_args self.a_flush = Signal() - self.f_pc = Signal(32) + self.f_pc = Signal(addr_wid) def elaborate(self, platform): m = Module() -- 2.30.2