From c8ff045fdbe4a1a9eddc4c36750a228cfb7770ba Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 3 Sep 2015 17:19:10 +0300 Subject: [PATCH] i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit According to the hardware docs a DC flush is sufficient to make CS_STALL happy, there's no need to add STALL_AT_SCOREBOARD whenever it's present. Reviewed-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index a2aef8ad2b6..ae3d8188325 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -36,6 +36,7 @@ * - Stall at Pixel Scoreboard * - Post-Sync Operation * - Depth Stall + * - DC Flush Enable * * I chose "Stall at Pixel Scoreboard" since we've used it effectively * in the past, but the choice is fairly arbitrary. @@ -49,7 +50,8 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags) PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_WRITE_TIMESTAMP | PIPE_CONTROL_STALL_AT_SCOREBOARD | - PIPE_CONTROL_DEPTH_STALL; + PIPE_CONTROL_DEPTH_STALL | + PIPE_CONTROL_DATA_CACHE_INVALIDATE; /* If we're doing a CS stall, and don't already have one of the * workaround bits set, add "Stall at Pixel Scoreboard." -- 2.30.2