From c9081a928a5ea257798a8e4d6fd381d4371ae9c8 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 23 Aug 2004 08:03:15 +0000 Subject: [PATCH] mips.md (UNSPEC_[LS][WD][LR]): Delete in favor of... * config/mips/mips.md (UNSPEC_[LS][WD][LR]): Delete in favor of... (UNSPEC_{LOAD,STORE}_{LEFT,RIGHT}): ...these new constants. Shuffle later constants to cover the gap. (load, store): New mode attributes. (mov_l[wd]l, mov_l[wd]r, mov_s[wd]l, mov_s[wd]r): Redefine using :GPR. Use new unspec constants. From-SVN: r86414 --- gcc/ChangeLog | 9 +++ gcc/config/mips/mips.md | 121 +++++++++++++--------------------------- 2 files changed, 47 insertions(+), 83 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fee94df1216..16cb707726b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2004-08-23 Richard Sandiford + + * config/mips/mips.md (UNSPEC_[LS][WD][LR]): Delete in favor of... + (UNSPEC_{LOAD,STORE}_{LEFT,RIGHT}): ...these new constants. Shuffle + later constants to cover the gap. + (load, store): New mode attributes. + (mov_l[wd]l, mov_l[wd]r, mov_s[wd]l, mov_s[wd]r): Redefine using :GPR. + Use new unspec constants. + 2004-08-23 Richard Sandiford * config/mips/mips.md (one_cmpl[sd]i2): Redefine using :GPR. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 20488d3aa82..14f3dbda2a8 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -36,19 +36,15 @@ (UNSPEC_CONSTTABLE_FLOAT 9) (UNSPEC_ALIGN 14) (UNSPEC_HIGH 17) - (UNSPEC_LWL 18) - (UNSPEC_LWR 19) - (UNSPEC_SWL 20) - (UNSPEC_SWR 21) - (UNSPEC_LDL 22) - (UNSPEC_LDR 23) - (UNSPEC_SDL 24) - (UNSPEC_SDR 25) - (UNSPEC_LOADGP 26) - (UNSPEC_LOAD_CALL 27) - (UNSPEC_LOAD_GOT 28) - (UNSPEC_GP 29) - (UNSPEC_MFHILO 30) + (UNSPEC_LOAD_LEFT 18) + (UNSPEC_LOAD_RIGHT 19) + (UNSPEC_STORE_LEFT 20) + (UNSPEC_STORE_RIGHT 21) + (UNSPEC_LOADGP 22) + (UNSPEC_LOAD_CALL 23) + (UNSPEC_LOAD_GOT 24) + (UNSPEC_GP 25) + (UNSPEC_MFHILO 26) (UNSPEC_ADDRESS_FIRST 100) @@ -297,6 +293,10 @@ ;; 32-bit version and "dsubu" in the 64-bit version. (define_mode_attr d [(SI "") (DI "d")]) +;; Mode attributes for GPR loads and stores. +(define_mode_attr load [(SI "lw") (DI "ld")]) +(define_mode_attr store [(SI "sw") (DI "sd")]) + ;; The unextended ranges of the MIPS16 addiu and daddiu instructions ;; are different. Some forms of unextended addiu have an 8-bit immediate ;; field but the equivalent daddiu has only a 5-bit field. @@ -3203,93 +3203,48 @@ beq\t%2,%.,1b\;\ ;; This allows us to use the standard length calculations for the "load" ;; and "store" type attributes. -(define_insn "mov_lwl" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec:SI [(match_operand:BLK 1 "memory_operand" "m") - (match_operand:QI 2 "memory_operand" "m")] - UNSPEC_LWL))] +(define_insn "mov_l" + [(set (match_operand:GPR 0 "register_operand" "=d") + (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") + (match_operand:QI 2 "memory_operand" "m")] + UNSPEC_LOAD_LEFT))] "!TARGET_MIPS16" - "lwl\t%0,%2" + "l\t%0,%2" [(set_attr "type" "load") - (set_attr "mode" "SI") + (set_attr "mode" "") (set_attr "hazard" "none")]) -(define_insn "mov_lwr" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec:SI [(match_operand:BLK 1 "memory_operand" "m") - (match_operand:QI 2 "memory_operand" "m") - (match_operand:SI 3 "register_operand" "0")] - UNSPEC_LWR))] +(define_insn "mov_r" + [(set (match_operand:GPR 0 "register_operand" "=d") + (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") + (match_operand:QI 2 "memory_operand" "m") + (match_operand:GPR 3 "register_operand" "0")] + UNSPEC_LOAD_RIGHT))] "!TARGET_MIPS16" - "lwr\t%0,%2" + "r\t%0,%2" [(set_attr "type" "load") - (set_attr "mode" "SI")]) - + (set_attr "mode" "")]) -(define_insn "mov_swl" +(define_insn "mov_l" [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ") + (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") (match_operand:QI 2 "memory_operand" "m")] - UNSPEC_SWL))] + UNSPEC_STORE_LEFT))] "!TARGET_MIPS16" - "swl\t%z1,%2" + "l\t%z1,%2" [(set_attr "type" "store") - (set_attr "mode" "SI")]) + (set_attr "mode" "")]) -(define_insn "mov_swr" +(define_insn "mov_r" [(set (match_operand:BLK 0 "memory_operand" "+m") - (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ") + (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") (match_operand:QI 2 "memory_operand" "m") (match_dup 0)] - UNSPEC_SWR))] + UNSPEC_STORE_RIGHT))] "!TARGET_MIPS16" - "swr\t%z1,%2" + "r\t%z1,%2" [(set_attr "type" "store") - (set_attr "mode" "SI")]) - - -(define_insn "mov_ldl" - [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:BLK 1 "memory_operand" "m") - (match_operand:QI 2 "memory_operand" "m")] - UNSPEC_LDL))] - "TARGET_64BIT && !TARGET_MIPS16" - "ldl\t%0,%2" - [(set_attr "type" "load") - (set_attr "mode" "DI")]) - -(define_insn "mov_ldr" - [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:BLK 1 "memory_operand" "m") - (match_operand:QI 2 "memory_operand" "m") - (match_operand:DI 3 "register_operand" "0")] - UNSPEC_LDR))] - "TARGET_64BIT && !TARGET_MIPS16" - "ldr\t%0,%2" - [(set_attr "type" "load") - (set_attr "mode" "DI")]) - - -(define_insn "mov_sdl" - [(set (match_operand:BLK 0 "memory_operand" "=m") - (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ") - (match_operand:QI 2 "memory_operand" "m")] - UNSPEC_SDL))] - "TARGET_64BIT && !TARGET_MIPS16" - "sdl\t%z1,%2" - [(set_attr "type" "store") - (set_attr "mode" "DI")]) - -(define_insn "mov_sdr" - [(set (match_operand:BLK 0 "memory_operand" "+m") - (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ") - (match_operand:QI 2 "memory_operand" "m") - (match_dup 0)] - UNSPEC_SDR))] - "TARGET_64BIT && !TARGET_MIPS16" - "sdr\t%z1,%2" - [(set_attr "type" "store") - (set_attr "mode" "DI")]) + (set_attr "mode" "")]) ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL. ;; The required value is: -- 2.30.2