From c90f46700dd2739ed9abb1246880d4829fdb3252 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 25 Jun 2019 14:28:10 +0200 Subject: [PATCH] radv/gfx10: mask DCC tile swizzle by alignment DCC alignment can be less than the alignment of the main surface. In that case, the DCC tile swizzle needs to be masked accordingly. Should have no impact on pre-gfx10. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 1f956e59954..f35d6ec4c32 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -4423,8 +4423,11 @@ radv_initialise_color_surface(struct radv_device *device, device->physical_device->rad_info.chip_class <= GFX8) va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset; + unsigned dcc_tile_swizzle = surf->tile_swizzle; + dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8; + cb->cb_dcc_base = va >> 8; - cb->cb_dcc_base |= surf->tile_swizzle; + cb->cb_dcc_base |= dcc_tile_swizzle; /* GFX10 field has the same base shift as the GFX6 field. */ uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; -- 2.30.2