From c917dce421110da9a14597dc680f237dac454f29 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Mar 2022 13:57:02 +0100
Subject: [PATCH] add cs_latch as a peer of bus_latch in case the address
 changes add a "ck_active" signal in hyperram.py

---
 lambdasoc/periph/hyperram.py | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index b8bff73..c992a29 100644
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -170,6 +170,7 @@ class HyperRAM(Peripheral, Elaboratable):
 
         ck       = self.phy.ck
         clk_phase = Signal(2)
+        ck_active = Signal()
         cs        = self.phy.cs
         ca        = Signal(48)
         ca_active = Signal()
@@ -188,7 +189,7 @@ class HyperRAM(Peripheral, Elaboratable):
         sync += clk_phase.eq(clk_phase + 1)
         with m.Switch(clk_phase):
             with m.Case(1):
-                sync += ck.eq(cs)
+                sync += ck.eq(ck_active)
             with m.Case(3):
                 sync += ck.eq(0)
 
@@ -229,12 +230,14 @@ class HyperRAM(Peripheral, Elaboratable):
         bus_we    = Signal()
         bus_sel   = Signal(4)
         bus_latch = Signal()
+        cs_latch  = Signal.like(cs)
         with m.If(bus_latch):
             with m.If(bus.we):
                 sync += sr.eq(Cat(Const(0, 16), bus.dat_w))
             sync += [ bus_we.eq(bus.we),
                       bus_sel.eq(bus.sel),
-                      bus_adr.eq(bus.adr)
+                      bus_adr.eq(bus.adr),
+                      cs_latch.eq(cs)
                     ]
 
 
@@ -266,6 +269,7 @@ class HyperRAM(Peripheral, Elaboratable):
             with m.State("SEND-COMMAND-ADDRESS"):
                 sync += cycles.eq(cycles+1)
                 comb += cs.eq(1)        # Set CSn.
+                comb += ck_active.eq(1) # Activate clock
                 comb += ca_active.eq(1) # Send Command on DQ.
                 comb += dq_oe.eq(1),    # Wait for 6*2 cycles...
                 with m.If(cycles == (6*2 - 1)):
@@ -274,10 +278,11 @@ class HyperRAM(Peripheral, Elaboratable):
 
             with m.State("WAIT-LATENCY"):
                 sync += cycles.eq(cycles+1)
-                comb += cs.eq(1) # Set CSn.
+                comb += cs.eq(1) # Set CSn directly (not via latch)
+                comb += ck_active.eq(1) # Activate clock
                 # Wait for Latency cycles...
                 with m.If(cycles == (latency_cycles - 1)):
-                    comb += bus_latch.eq(1) # Latch Bus.
+                    comb += bus_latch.eq(1) # Latch Bus (and cs)
                     # Early Write Ack (to allow bursting).
                     comb += bus.ack.eq(bus.we)
                     m.next = "READ-WRITE-DATA0"
@@ -287,7 +292,8 @@ class HyperRAM(Peripheral, Elaboratable):
             for n in range(states):
                 with m.State("READ-WRITE-DATA%d" % n):
                     sync += cycles.eq(cycles+1)
-                    comb += cs.eq(1), # Set CSn.
+                    comb += cs.eq(cs_latch), # Set CSn from Latch
+                    comb += ck_active.eq(1) # Activate clock
                     # Send Data on DQ/RWDS (for write).
                     with m.If(bus_we):
                         comb += dq_oe.eq(1)
@@ -308,13 +314,14 @@ class HyperRAM(Peripheral, Elaboratable):
                             with m.If(bus.stb & bus.cyc & 
                                       (bus.we == bus_we) & 
                                       (bus.adr == (bus_adr + 1))):
-                                comb += bus_latch.eq(1), # Latch Bus.
+                                comb += bus_latch.eq(1), # Latch Bus (and cs)
                                 # Early Write Ack (to allow bursting).
                                 comb += bus.ack.eq(bus.we)
                             # Else end the burst.
                             with m.Elif(bus_we | nfirst):
                                 m.next = "IDLE"
-                                sync += cycles.eq(0)
+                                sync += cycles.eq(0)   # reset to start
+                                sync += cs_latch.eq(0) # helps debugging
                         # Read Ack (when dat_r ready).
                         if n == 0:
                             comb += bus.ack.eq(nfirst & ~bus_we)
-- 
2.30.2