From c91b473f97c9d3a28c43ab6451b206082057a24a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 7 Apr 2022 11:29:14 +0100 Subject: [PATCH] doh --- src/nmigen_gf/hdl/cldivrem.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py index 973e0c9..43257e7 100644 --- a/src/nmigen_gf/hdl/cldivrem.py +++ b/src/nmigen_gf/hdl/cldivrem.py @@ -98,7 +98,7 @@ class EqualLeadingZeroCount(Elaboratable): csum = Signal(self.width + 1) carry_in = 1 # both have no leading zeros so far, so set carry - m.d.comb += sum.eq(addend1 + addend2 + carry_in) + m.d.comb += csum.eq(addend1 + addend2 + carry_in) m.d.comb += self.out.eq(csum[self.width]) # out is carry-out return m -- 2.30.2