From c91e9f7066acdd22b6e6f6d3a96fca9c770cbdfc Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 11 Dec 2020 02:16:24 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index edb6802fd..d1e0e2efd 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -77,6 +77,8 @@ If there are spare bits it would be very good to look at using some of them to s Idea: 2 bits for clamping mode? similar to elwidth: + + * 0b00 default (no clamp) * 0b01 8 bit (sel: -128/127, us:0/255) * 0b10 16 bit @@ -98,3 +100,8 @@ with 2x12 this would mean no need to have complex encoding of swizzle. if we really do need 2 bits spare then the complex encoder of swizzle could be deployed. +# note about INT predicate + +001 ALWAYS (implicit) Operation is not masked + +this means by default that 001 will always be in nonpredicated ops, which seems anomalous. would 000 be better to indicate "no predication"? -- 2.30.2