From c956ca0842f03cc820e9f819336d560f4eb1d0ab Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 Jun 2019 08:48:57 +0100 Subject: [PATCH] initialise SUBVL to 1 --- riscv/processor.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index c93c2e5..581c549 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -143,6 +143,14 @@ void state_t::reset(reg_t max_isa) msv.state_size = 1; ssv.state_size = 1; usv.state_size = 3; + // VL and MVL all 0 + msv.vl = msv.mvl = 0; + ssv.vl = ssv.mvl = 0; + usv.vl = usv.mvl = 0; + // SUBVL all 1 + msv.subvl = 1; + ssv.subvl = 1; + usv.subvl = 1; #endif } -- 2.30.2