From c957249df9d09c269425e46afc62dc706826cad6 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 16 Jun 2020 12:30:28 -0400 Subject: [PATCH] pan/mdg: Skip r1.w write where possible MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Should help cycle count. Register pressure is spurious here. total instructions in shared programs: 50501 -> 49517 (-1.95%) instructions in affected programs: 33342 -> 32358 (-2.95%) helped: 393 HURT: 0 helped stats (abs) min: 2 max: 3 x̄: 2.50 x̃: 3 helped stats (rel) min: 0.26% max: 33.33% x̄: 11.99% x̃: 9.09% 95% mean confidence interval for instructions value: -2.55 -2.45 95% mean confidence interval for instructions %-change: -13.01% -10.97% Instructions are helped. total bundles in shared programs: 25511 -> 25309 (-0.79%) bundles in affected programs: 7778 -> 7576 (-2.60%) helped: 202 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.43% max: 20.00% x̄: 5.97% x̃: 4.35% 95% mean confidence interval for bundles value: -1.00 -1.00 95% mean confidence interval for bundles %-change: -6.65% -5.28% Bundles are helped. total quadwords in shared programs: 40789 -> 40339 (-1.10%) quadwords in affected programs: 25453 -> 25003 (-1.77%) helped: 273 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 1.65 x̃: 2 helped stats (rel) min: 0.16% max: 22.22% x̄: 5.99% x̃: 3.92% 95% mean confidence interval for quadwords value: -1.71 -1.59 95% mean confidence interval for quadwords %-change: -6.68% -5.30% Quadwords are helped. total registers in shared programs: 3911 -> 3784 (-3.25%) registers in affected programs: 275 -> 148 (-46.18%) helped: 129 HURT: 2 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 14.29% max: 50.00% x̄: 48.69% x̃: 50.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00% 95% mean confidence interval for registers value: -1.01 -0.93 95% mean confidence interval for registers %-change: -49.45% -44.91% Registers are helped. total threads in shared programs: 2455 -> 2455 (0.00%) threads in affected programs: 0 -> 0 helped: 0 HURT: 0 Part-of: --- src/panfrost/midgard/midgard_schedule.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 590468b40a0..3aee91222ef 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -1087,7 +1087,14 @@ mir_schedule_alu( bundle.last_writeout = branch->last_writeout; } - if (writeout) { + /* When MRT is in use, writeout loops require r1.w to be filled (with a + * return address? by symmetry with Bifrost, etc), at least for blend + * shaders to work properly. When MRT is not in use (including on SFBD + * GPUs), this is not needed. Blend shaders themselves don't know if + * they are paired with MRT or not so they always need this, at least + * on MFBD GPUs. */ + + if (writeout && (ctx->is_blend || ctx->writeout_branch[1])) { vadd = ralloc(ctx, midgard_instruction); *vadd = v_mov(~0, make_compiler_temp(ctx)); -- 2.30.2