From c95ea6eb7b6cd75de7200778bd36bbb3db19bb3c Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Thu, 7 Apr 2022 13:38:59 -0500 Subject: [PATCH] Switch CRG back over to ECP5 version Memtest pass using external UART bridge --- examples/headless-versa-85.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/headless-versa-85.py b/examples/headless-versa-85.py index 24cb4d0..d2692e5 100644 --- a/examples/headless-versa-85.py +++ b/examples/headless-versa-85.py @@ -19,8 +19,8 @@ from gram.modules import MT41K64M16 from gram.frontend.wishbone import gramWishbone from nmigen_boards.versa_ecp5 import VersaECP5Platform85 -#from ecp5_crg import ECP5CRG -from crg import ECPIX5CRG +from ecp5_crg import ECP5CRG +#from crg import ECPIX5CRG from uartbridge import UARTBridge from crg import * @@ -31,8 +31,8 @@ class DDR3SoC(SoC, Elaboratable): self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8, features={"cti", "bte"}) - self.crg = ECPIX5CRG() - #self.crg = ECP5CRG() + #self.crg = ECPIX5CRG() + self.crg = ECP5CRG() self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0)) -- 2.30.2