From c96490e3b5ea0e369837dbb8067cf3d6b0d6b767 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 30 Jul 2012 14:21:16 +0000 Subject: [PATCH] radeon/llvm: Remove IL_cmp DAG node --- src/gallium/drivers/radeon/AMDIL.h | 75 ---- .../drivers/radeon/AMDILISelLowering.cpp | 342 +----------------- .../drivers/radeon/AMDILISelLowering.h | 7 - src/gallium/drivers/radeon/AMDILInstrInfo.td | 80 ---- 4 files changed, 2 insertions(+), 502 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDIL.h b/src/gallium/drivers/radeon/AMDIL.h index 34f32ffe37f..b446b68b46e 100644 --- a/src/gallium/drivers/radeon/AMDIL.h +++ b/src/gallium/drivers/radeon/AMDIL.h @@ -167,80 +167,5 @@ typedef union ResourceRec { } // namespace AMDILAS -// Enums corresponding to AMDIL condition codes for IL. These -// values must be kept in sync with the ones in the .td file. -namespace AMDILCC { -enum CondCodes { - // AMDIL specific condition codes. These correspond to the IL_CC_* - // in AMDILInstrInfo.td and must be kept in the same order. - IL_CC_D_EQ = 0, // DEQ instruction. - IL_CC_D_GE = 1, // DGE instruction. - IL_CC_D_LT = 2, // DLT instruction. - IL_CC_D_NE = 3, // DNE instruction. - IL_CC_F_EQ = 4, // EQ instruction. - IL_CC_F_GE = 5, // GE instruction. - IL_CC_F_LT = 6, // LT instruction. - IL_CC_F_NE = 7, // NE instruction. - IL_CC_I_EQ = 8, // IEQ instruction. - IL_CC_I_GE = 9, // IGE instruction. - IL_CC_I_LT = 10, // ILT instruction. - IL_CC_I_NE = 11, // INE instruction. - IL_CC_U_GE = 12, // UGE instruction. - IL_CC_U_LT = 13, // ULE instruction. - // Pseudo IL Comparison instructions here. - IL_CC_F_GT = 14, // GT instruction. - IL_CC_U_GT = 15, - IL_CC_I_GT = 16, - IL_CC_D_GT = 17, - IL_CC_F_LE = 18, // LE instruction - IL_CC_U_LE = 19, - IL_CC_I_LE = 20, - IL_CC_D_LE = 21, - IL_CC_F_UNE = 22, - IL_CC_F_UEQ = 23, - IL_CC_F_ULT = 24, - IL_CC_F_UGT = 25, - IL_CC_F_ULE = 26, - IL_CC_F_UGE = 27, - IL_CC_F_ONE = 28, - IL_CC_F_OEQ = 29, - IL_CC_F_OLT = 30, - IL_CC_F_OGT = 31, - IL_CC_F_OLE = 32, - IL_CC_F_OGE = 33, - IL_CC_D_UNE = 34, - IL_CC_D_UEQ = 35, - IL_CC_D_ULT = 36, - IL_CC_D_UGT = 37, - IL_CC_D_ULE = 38, - IL_CC_D_UGE = 39, - IL_CC_D_ONE = 40, - IL_CC_D_OEQ = 41, - IL_CC_D_OLT = 42, - IL_CC_D_OGT = 43, - IL_CC_D_OLE = 44, - IL_CC_D_OGE = 45, - IL_CC_U_EQ = 46, - IL_CC_U_NE = 47, - IL_CC_F_O = 48, - IL_CC_D_O = 49, - IL_CC_F_UO = 50, - IL_CC_D_UO = 51, - IL_CC_L_LE = 52, - IL_CC_L_GE = 53, - IL_CC_L_EQ = 54, - IL_CC_L_NE = 55, - IL_CC_L_LT = 56, - IL_CC_L_GT = 57, - IL_CC_UL_LE = 58, - IL_CC_UL_GE = 59, - IL_CC_UL_EQ = 60, - IL_CC_UL_NE = 61, - IL_CC_UL_LT = 62, - IL_CC_UL_GT = 63, - COND_ERROR = 64 -}; - -} // end namespace AMDILCC } // end namespace llvm #endif // AMDIL_H_ diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index c9fd4a1902b..f5f756199d9 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -85,333 +85,6 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) } return Src; } -// CondCCodeToCC - Convert a DAG condition code to a AMDIL CC -// condition. - static AMDILCC::CondCodes -CondCCodeToCC(ISD::CondCode CC, const MVT::SimpleValueType& type) -{ - switch (CC) { - default: - { - errs()<<"Condition Code: "<< (unsigned int)CC<<"\n"; - assert(0 && "Unknown condition code!"); - } - case ISD::SETO: - switch(type) { - case MVT::f32: - return AMDILCC::IL_CC_F_O; - case MVT::f64: - return AMDILCC::IL_CC_D_O; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETUO: - switch(type) { - case MVT::f32: - return AMDILCC::IL_CC_F_UO; - case MVT::f64: - return AMDILCC::IL_CC_D_UO; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETGT: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_GT; - case MVT::f32: - return AMDILCC::IL_CC_F_GT; - case MVT::f64: - return AMDILCC::IL_CC_D_GT; - case MVT::i64: - return AMDILCC::IL_CC_L_GT; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETGE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_GE; - case MVT::f32: - return AMDILCC::IL_CC_F_GE; - case MVT::f64: - return AMDILCC::IL_CC_D_GE; - case MVT::i64: - return AMDILCC::IL_CC_L_GE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETLT: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_LT; - case MVT::f32: - return AMDILCC::IL_CC_F_LT; - case MVT::f64: - return AMDILCC::IL_CC_D_LT; - case MVT::i64: - return AMDILCC::IL_CC_L_LT; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETLE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_LE; - case MVT::f32: - return AMDILCC::IL_CC_F_LE; - case MVT::f64: - return AMDILCC::IL_CC_D_LE; - case MVT::i64: - return AMDILCC::IL_CC_L_LE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETNE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_NE; - case MVT::f32: - return AMDILCC::IL_CC_F_NE; - case MVT::f64: - return AMDILCC::IL_CC_D_NE; - case MVT::i64: - return AMDILCC::IL_CC_L_NE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETEQ: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_I_EQ; - case MVT::f32: - return AMDILCC::IL_CC_F_EQ; - case MVT::f64: - return AMDILCC::IL_CC_D_EQ; - case MVT::i64: - return AMDILCC::IL_CC_L_EQ; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETUGT: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_GT; - case MVT::f32: - return AMDILCC::IL_CC_F_UGT; - case MVT::f64: - return AMDILCC::IL_CC_D_UGT; - case MVT::i64: - return AMDILCC::IL_CC_UL_GT; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETUGE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_GE; - case MVT::f32: - return AMDILCC::IL_CC_F_UGE; - case MVT::f64: - return AMDILCC::IL_CC_D_UGE; - case MVT::i64: - return AMDILCC::IL_CC_UL_GE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETULT: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_LT; - case MVT::f32: - return AMDILCC::IL_CC_F_ULT; - case MVT::f64: - return AMDILCC::IL_CC_D_ULT; - case MVT::i64: - return AMDILCC::IL_CC_UL_LT; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETULE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_LE; - case MVT::f32: - return AMDILCC::IL_CC_F_ULE; - case MVT::f64: - return AMDILCC::IL_CC_D_ULE; - case MVT::i64: - return AMDILCC::IL_CC_UL_LE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETUNE: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_NE; - case MVT::f32: - return AMDILCC::IL_CC_F_UNE; - case MVT::f64: - return AMDILCC::IL_CC_D_UNE; - case MVT::i64: - return AMDILCC::IL_CC_UL_NE; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETUEQ: - switch (type) { - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - return AMDILCC::IL_CC_U_EQ; - case MVT::f32: - return AMDILCC::IL_CC_F_UEQ; - case MVT::f64: - return AMDILCC::IL_CC_D_UEQ; - case MVT::i64: - return AMDILCC::IL_CC_UL_EQ; - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETOGT: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_OGT; - case MVT::f64: - return AMDILCC::IL_CC_D_OGT; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETOGE: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_OGE; - case MVT::f64: - return AMDILCC::IL_CC_D_OGE; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETOLT: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_OLT; - case MVT::f64: - return AMDILCC::IL_CC_D_OLT; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETOLE: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_OLE; - case MVT::f64: - return AMDILCC::IL_CC_D_OLE; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETONE: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_ONE; - case MVT::f64: - return AMDILCC::IL_CC_D_ONE; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - case ISD::SETOEQ: - switch (type) { - case MVT::f32: - return AMDILCC::IL_CC_F_OEQ; - case MVT::f64: - return AMDILCC::IL_CC_D_OEQ; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - default: - assert(0 && "Opcode combination not generated correctly!"); - return AMDILCC::COND_ERROR; - }; - }; -} //===----------------------------------------------------------------------===// // TargetLowering Implementation Help Functions End @@ -632,13 +305,6 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const case AMDILISD::UMUL: return "AMDILISD::UMUL"; case AMDILISD::DIV_INF: return "AMDILISD::DIV_INF"; case AMDILISD::VBUILD: return "AMDILISD::VBUILD"; - case AMDILISD::CMP: return "AMDILISD::CMP"; - case AMDILISD::IL_CC_I_LT: return "AMDILISD::IL_CC_I_LT"; - case AMDILISD::IL_CC_I_LE: return "AMDILISD::IL_CC_I_LE"; - case AMDILISD::IL_CC_I_GT: return "AMDILISD::IL_CC_I_GT"; - case AMDILISD::IL_CC_I_GE: return "AMDILISD::IL_CC_I_GE"; - case AMDILISD::IL_CC_I_EQ: return "AMDILISD::IL_CC_I_EQ"; - case AMDILISD::IL_CC_I_NE: return "AMDILISD::IL_CC_I_NE"; case AMDILISD::RET_FLAG: return "AMDILISD::RET_FLAG"; case AMDILISD::BRANCH_COND: return "AMDILISD::BRANCH_COND"; @@ -1162,14 +828,10 @@ AMDILTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const SDValue r1 = RHS; // ilt r10, r0, 0 - SDValue r10 = DAG.getNode(AMDILISD::CMP, DL, OVT, - DAG.getConstant(CondCCodeToCC(ISD::SETLT, MVT::i32), MVT::i32), - r0, DAG.getConstant(0, OVT)); + SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); // ilt r11, r1, 0 - SDValue r11 = DAG.getNode(AMDILISD::CMP, DL, OVT, - DAG.getConstant(CondCCodeToCC(ISD::SETLT, MVT::i32), MVT::i32), - r1, DAG.getConstant(0, OVT)); + SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); // iadd r0, r0, r10 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10); diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.h b/src/gallium/drivers/radeon/AMDILISelLowering.h index 9a4ae1cec07..e660492656f 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.h +++ b/src/gallium/drivers/radeon/AMDILISelLowering.h @@ -34,13 +34,6 @@ namespace llvm SELECT_CC, // Select the correct conditional instruction UMUL, // 32bit unsigned multiplication DIV_INF, // Divide with infinity returned on zero divisor - CMP, - IL_CC_I_GT, - IL_CC_I_LT, - IL_CC_I_GE, - IL_CC_I_LE, - IL_CC_I_EQ, - IL_CC_I_NE, RET_FLAG, BRANCH_COND, LAST_ISD_NUMBER diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td index ad7f618be52..e9e87b7c2ac 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.td +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td @@ -96,10 +96,6 @@ def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [ def SDTIL_BRCond : SDTypeProfile<0, 2, [ SDTCisVT<0, OtherVT> ]>; -// Comparison instruction -def SDTIL_Cmp : SDTypeProfile<1, 3, [ - SDTCisSameAs<0, 2>, SDTCisSameAs<2,3>, SDTCisVT<1, i32> - ]>; //===--------------------------------------------------------------------===// // Custom Selection DAG Nodes @@ -109,11 +105,6 @@ def SDTIL_Cmp : SDTypeProfile<1, 3, [ //===----------------------------------------------------------------------===// def IL_brcond : SDNode<"AMDILISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; -//===----------------------------------------------------------------------===// -// Comparison DAG Nodes -//===----------------------------------------------------------------------===// -def IL_cmp : SDNode<"AMDILISD::CMP", SDTIL_Cmp>; - //===----------------------------------------------------------------------===// // Call/Return DAG Nodes //===----------------------------------------------------------------------===// @@ -168,77 +159,6 @@ def ADDRF : ComplexPattern; def ADDR64 : ComplexPattern; def ADDR64F : ComplexPattern; - -//===----------------------------------------------------------------------===// -// Conditional Instruction Pattern Leafs -//===----------------------------------------------------------------------===// -class IL_CC_Op : PatLeaf<(i32 N)>; -def IL_CC_D_EQ : IL_CC_Op<0>; -def IL_CC_D_GE : IL_CC_Op<1>; -def IL_CC_D_LT : IL_CC_Op<2>; -def IL_CC_D_NE : IL_CC_Op<3>; -def IL_CC_F_EQ : IL_CC_Op<4>; -def IL_CC_F_GE : IL_CC_Op<5>; -def IL_CC_F_LT : IL_CC_Op<6>; -def IL_CC_F_NE : IL_CC_Op<7>; -def IL_CC_I_EQ : IL_CC_Op<8>; -def IL_CC_I_GE : IL_CC_Op<9>; -def IL_CC_I_LT : IL_CC_Op<10>; -def IL_CC_I_NE : IL_CC_Op<11>; -def IL_CC_U_GE : IL_CC_Op<12>; -def IL_CC_U_LT : IL_CC_Op<13>; -// Pseudo IL comparison instructions that aren't natively supported -def IL_CC_F_GT : IL_CC_Op<14>; -def IL_CC_U_GT : IL_CC_Op<15>; -def IL_CC_I_GT : IL_CC_Op<16>; -def IL_CC_D_GT : IL_CC_Op<17>; -def IL_CC_F_LE : IL_CC_Op<18>; -def IL_CC_U_LE : IL_CC_Op<19>; -def IL_CC_I_LE : IL_CC_Op<20>; -def IL_CC_D_LE : IL_CC_Op<21>; -def IL_CC_F_UNE : IL_CC_Op<22>; -def IL_CC_F_UEQ : IL_CC_Op<23>; -def IL_CC_F_ULT : IL_CC_Op<24>; -def IL_CC_F_UGT : IL_CC_Op<25>; -def IL_CC_F_ULE : IL_CC_Op<26>; -def IL_CC_F_UGE : IL_CC_Op<27>; -def IL_CC_F_ONE : IL_CC_Op<28>; -def IL_CC_F_OEQ : IL_CC_Op<29>; -def IL_CC_F_OLT : IL_CC_Op<30>; -def IL_CC_F_OGT : IL_CC_Op<31>; -def IL_CC_F_OLE : IL_CC_Op<32>; -def IL_CC_F_OGE : IL_CC_Op<33>; -def IL_CC_D_UNE : IL_CC_Op<34>; -def IL_CC_D_UEQ : IL_CC_Op<35>; -def IL_CC_D_ULT : IL_CC_Op<36>; -def IL_CC_D_UGT : IL_CC_Op<37>; -def IL_CC_D_ULE : IL_CC_Op<38>; -def IL_CC_D_UGE : IL_CC_Op<39>; -def IL_CC_D_ONE : IL_CC_Op<30>; -def IL_CC_D_OEQ : IL_CC_Op<41>; -def IL_CC_D_OLT : IL_CC_Op<42>; -def IL_CC_D_OGT : IL_CC_Op<43>; -def IL_CC_D_OLE : IL_CC_Op<44>; -def IL_CC_D_OGE : IL_CC_Op<45>; -def IL_CC_U_EQ : IL_CC_Op<46>; -def IL_CC_U_NE : IL_CC_Op<47>; -def IL_CC_F_O : IL_CC_Op<48>; -def IL_CC_D_O : IL_CC_Op<49>; -def IL_CC_F_UO : IL_CC_Op<50>; -def IL_CC_D_UO : IL_CC_Op<51>; -def IL_CC_L_LE : IL_CC_Op<52>; -def IL_CC_L_GE : IL_CC_Op<53>; -def IL_CC_L_EQ : IL_CC_Op<54>; -def IL_CC_L_NE : IL_CC_Op<55>; -def IL_CC_L_LT : IL_CC_Op<56>; -def IL_CC_L_GT : IL_CC_Op<57>; -def IL_CC_UL_LE : IL_CC_Op<58>; -def IL_CC_UL_GE : IL_CC_Op<59>; -def IL_CC_UL_EQ : IL_CC_Op<60>; -def IL_CC_UL_NE : IL_CC_Op<61>; -def IL_CC_UL_LT : IL_CC_Op<62>; -def IL_CC_UL_GT : IL_CC_Op<63>; - //===----------------------------------------------------------------------===// // Instruction format classes //===----------------------------------------------------------------------===// -- 2.30.2