From c9693e96d4921c6abe1ff9c0a48022962206fced Mon Sep 17 00:00:00 2001 From: Larin Hennessy Date: Mon, 23 Dec 2002 23:02:49 +0000 Subject: [PATCH] install.texi: Remove i386-*-isc, i860-*-bsd, m68k-altos-sysv, m68k-isi-bsd, m68k-sony-bsd entries. 2002-12-23 Larin Hennessy * doc/install.texi: Remove i386-*-isc, i860-*-bsd, m68k-altos-sysv, m68k-isi-bsd, m68k-sony-bsd entries. * doc/invoke.texi: Remove AMD 29K, ARM RISC/iX, Clipper, Convex, DG/UX entries. * doc/md.texi: Remove AMD 29K entries. * doc/trouble.texi: Remove Alliant, DG/UX, Iris 4.0.5F, GAS 1.38.1, NewsOS, RT PC, WE32K entries. From-SVN: r60455 --- gcc/ChangeLog | 10 ++ gcc/doc/install.texi | 8 +- gcc/doc/invoke.texi | 261 +------------------------------------------ gcc/doc/md.texi | 57 +--------- gcc/doc/trouble.texi | 73 ------------ 5 files changed, 19 insertions(+), 390 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6fd530633cd..c0463834774 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2002-12-23 Larin Hennessy + + * doc/install.texi: Remove i386-*-isc, i860-*-bsd, + m68k-altos-sysv, m68k-isi-bsd, m68k-sony-bsd entries. + * doc/invoke.texi: Remove AMD 29K, ARM RISC/iX, Clipper, Convex, + DG/UX entries. + * doc/md.texi: Remove AMD 29K entries. + * doc/trouble.texi: Remove Alliant, DG/UX, Iris 4.0.5F, GAS + 1.38.1, NewsOS, RT PC, WE32K entries. + 2002-12-23 Aldy Hernandez PR/8763 diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index c3958382144..f6e8cfa895f 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -559,12 +559,8 @@ whether you use the GNU assembler. On any other system, @item @samp{hppa1.0-@var{any}-@var{any}} @item @samp{hppa1.1-@var{any}-@var{any}} @item @samp{i386-@var{any}-sysv} -@item @samp{i386-@var{any}-isc} -@item @samp{i860-@var{any}-bsd} @item @samp{m68k-bull-sysv} @item @samp{m68k-hp-hpux} -@item @samp{m68k-sony-bsd} -@item @samp{m68k-altos-sysv} @item @samp{m68000-hp-hpux} @item @samp{m68000-att-sysv} @item @samp{@var{any}-lynx-lynxos} @@ -822,8 +818,8 @@ option. This option has no effect on the other hosts. @item --nfp Specify that the machine does not have a floating point unit. This -option only applies to @samp{m68k-sun-sunos@var{n}} and -@samp{m68k-isi-bsd}. On any other system, @option{--nfp} has no effect. +option only applies to @samp{m68k-sun-sunos@var{n}}. On any other +system, @option{--nfp} has no effect. @item --enable-checking @itemx --enable-checking=@var{list} diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8b602358b18..c1bfae47cce 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -367,22 +367,6 @@ in the following sections. -msoft-float -msoft-quad-float -msparclite -mstack-bias @gol -msupersparc -munaligned-doubles -mv8} -@emph{Convex Options} -@gccoptlist{ --mc1 -mc2 -mc32 -mc34 -mc38 @gol --margcount -mnoargcount @gol --mlong32 -mlong64 @gol --mvolatile-cache -mvolatile-nocache} - -@emph{AMD29K Options} -@gccoptlist{ --m29000 -m29050 -mbw -mnbw -mdw -mndw @gol --mlarge -mnormal -msmall @gol --mkernel-registers -mno-reuse-arg-regs @gol --mno-stack-check -mno-storem-bug @gol --mreuse-arg-regs -msoft-float -mstack-check @gol --mstorem-bug -muser-registers} - @emph{ARM Options} @gccoptlist{ -mapcs-frame -mno-apcs-frame @gol @@ -397,7 +381,6 @@ in the following sections. -mthumb-interwork -mno-thumb-interwork @gol -mcpu=@var{name} -march=@var{name} -mfpe=@var{name} @gol -mstructure-size-boundary=@var{n} @gol --mbsd -mxopen -mno-symrename @gol -mabort-on-noreturn @gol -mlong-calls -mno-long-calls @gol -msingle-pic-base -mno-single-pic-base @gol @@ -566,10 +549,6 @@ in the following sections. @gccoptlist{ -mvms-return-codes} -@emph{Clipper Options} -@gccoptlist{ --mc300 -mc400} - @emph{H8/300 Options} @gccoptlist{ -mrelax -mh -ms -mn -mint32 -malign-300} @@ -5252,8 +5231,6 @@ that macro, which enables you to change the defaults. * M68hc1x Options:: * VAX Options:: * SPARC Options:: -* Convex Options:: -* AMD29K Options:: * ARM Options:: * MN10200 Options:: * MN10300 Options:: @@ -5268,7 +5245,6 @@ that macro, which enables you to change the defaults. * Intel 960 Options:: * DEC Alpha Options:: * DEC Alpha/VMS Options:: -* Clipper Options:: * H8/300 Options:: * SH Options:: * System V Options:: @@ -5799,195 +5775,6 @@ when making stack frame references. Otherwise, assume no such offset is present. @end table -@node Convex Options -@subsection Convex Options -@cindex Convex options - -These @samp{-m} options are defined for Convex: - -@table @gcctabopt -@item -mc1 -@opindex mc1 -Generate output for C1. The code will run on any Convex machine. -The preprocessor symbol @code{__convex__c1__} is defined. - -@item -mc2 -@opindex mc2 -Generate output for C2. Uses instructions not available on C1. -Scheduling and other optimizations are chosen for max performance on C2. -The preprocessor symbol @code{__convex_c2__} is defined. - -@item -mc32 -@opindex mc32 -Generate output for C32xx. Uses instructions not available on C1. -Scheduling and other optimizations are chosen for max performance on C32. -The preprocessor symbol @code{__convex_c32__} is defined. - -@item -mc34 -@opindex mc34 -Generate output for C34xx. Uses instructions not available on C1. -Scheduling and other optimizations are chosen for max performance on C34. -The preprocessor symbol @code{__convex_c34__} is defined. - -@item -mc38 -@opindex mc38 -Generate output for C38xx. Uses instructions not available on C1. -Scheduling and other optimizations are chosen for max performance on C38. -The preprocessor symbol @code{__convex_c38__} is defined. - -@item -margcount -@opindex margcount -Generate code which puts an argument count in the word preceding each -argument list. This is compatible with regular CC, and a few programs -may need the argument count word. GDB and other source-level debuggers -do not need it; this info is in the symbol table. - -@item -mnoargcount -@opindex mnoargcount -Omit the argument count word. This is the default. - -@item -mvolatile-cache -@opindex mvolatile-cache -Allow volatile references to be cached. This is the default. - -@item -mvolatile-nocache -@opindex mvolatile-nocache -Volatile references bypass the data cache, going all the way to memory. -This is only needed for multi-processor code that does not use standard -synchronization instructions. Making non-volatile references to volatile -locations will not necessarily work. - -@item -mlong32 -@opindex mlong32 -Type long is 32 bits, the same as type int. This is the default. - -@item -mlong64 -@opindex mlong64 -Type long is 64 bits, the same as type long long. This option is useless, -because no library support exists for it. -@end table - -@node AMD29K Options -@subsection AMD29K Options -@cindex AMD29K options - -These @samp{-m} options are defined for the AMD Am29000: - -@table @gcctabopt -@item -mdw -@opindex mdw -@cindex DW bit (29k) -Generate code that assumes the @code{DW} bit is set, i.e., that byte and -halfword operations are directly supported by the hardware. This is the -default. - -@item -mndw -@opindex mndw -Generate code that assumes the @code{DW} bit is not set. - -@item -mbw -@opindex mbw -@cindex byte writes (29k) -Generate code that assumes the system supports byte and halfword write -operations. This is the default. - -@item -mnbw -@opindex mnbw -Generate code that assumes the systems does not support byte and -halfword write operations. @option{-mnbw} implies @option{-mndw}. - -@item -msmall -@opindex msmall -@cindex memory model (29k) -Use a small memory model that assumes that all function addresses are -either within a single 256 KB segment or at an absolute address of less -than 256k. This allows the @code{call} instruction to be used instead -of a @code{const}, @code{consth}, @code{calli} sequence. - -@item -mnormal -@opindex mnormal -Use the normal memory model: Generate @code{call} instructions only when -calling functions in the same file and @code{calli} instructions -otherwise. This works if each file occupies less than 256 KB but allows -the entire executable to be larger than 256 KB@. This is the default. - -@item -mlarge -@opindex mlarge -Always use @code{calli} instructions. Specify this option if you expect -a single file to compile into more than 256 KB of code. - -@item -m29050 -@opindex m29050 -@cindex processor selection (29k) -Generate code for the Am29050. - -@item -m29000 -@opindex m29000 -Generate code for the Am29000. This is the default. - -@item -mkernel-registers -@opindex mkernel-registers -@cindex kernel and user registers (29k) -Generate references to registers @code{gr64-gr95} instead of to -registers @code{gr96-gr127}. This option can be used when compiling -kernel code that wants a set of global registers disjoint from that used -by user-mode code. - -Note that when this option is used, register names in @samp{-f} flags -must use the normal, user-mode, names. - -@item -muser-registers -@opindex muser-registers -Use the normal set of global registers, @code{gr96-gr127}. This is the -default. - -@item -mstack-check -@itemx -mno-stack-check -@opindex mstack-check -@opindex mno-stack-check -@cindex stack checks (29k) -Insert (or do not insert) a call to @code{__msp_check} after each stack -adjustment. This is often used for kernel code. - -@item -mstorem-bug -@itemx -mno-storem-bug -@opindex mstorem-bug -@opindex mno-storem-bug -@cindex storem bug (29k) -@option{-mstorem-bug} handles 29k processors which cannot handle the -separation of a mtsrim insn and a storem instruction (most 29000 chips -to date, but not the 29050). - -@item -mno-reuse-arg-regs -@itemx -mreuse-arg-regs -@opindex mno-reuse-arg-regs -@opindex mreuse-arg-regs -@option{-mno-reuse-arg-regs} tells the compiler to only use incoming argument -registers for copying out arguments. This helps detect calling a function -with fewer arguments than it was declared with. - -@item -mno-impure-text -@itemx -mimpure-text -@opindex mno-impure-text -@opindex mimpure-text -@option{-mimpure-text}, used in addition to @option{-shared}, tells the compiler to -not pass @option{-assert pure-text} to the linker when linking a shared object. - -@item -msoft-float -@opindex msoft-float -Generate output containing library calls for floating point. -@strong{Warning:} the requisite libraries are not part of GCC@. -Normally the facilities of the machine's usual C compiler are used, but -this can't be done directly in cross-compilation. You must make your -own arrangements to provide suitable library functions for -cross-compilation. - -@item -mno-multm -@opindex mno-multm -Do not generate multm or multmu instructions. This is useful for some embedded -systems which do not have trap handlers for these instructions. -@end table - @node ARM Options @subsection ARM Options @cindex ARM options @@ -6152,25 +5939,6 @@ These are deprecated aliases for @option{-malignment-traps}. @opindex mshort-load-words This are deprecated aliases for @option{-mno-alignment-traps}. -@item -mbsd -@opindex mbsd -This option only applies to RISC iX@. Emulate the native BSD-mode -compiler. This is the default if @option{-ansi} is not specified. - -@item -mxopen -@opindex mxopen -This option only applies to RISC iX@. Emulate the native X/Open-mode -compiler. - -@item -mno-symrename -@opindex mno-symrename -This option only applies to RISC iX@. Do not run the assembler -post-processor, @samp{symrename}, after code has been assembled. -Normally it is necessary to modify some of the standard symbols in -preparation for linking with the RISC iX C library; this option -suppresses this pass. The post-processor is never run when the -compiler is built for cross-compilation. - @item -mcpu=@var{name} @opindex mcpu This specifies the name of the target ARM processor. GCC uses this name @@ -6512,9 +6280,9 @@ underscore as prefix on each name. Include (or omit) additional debugging information (about registers used in each stack frame) as specified in the 88open Object Compatibility Standard, ``OCS''@. This extra information allows debugging of code that -has had the frame pointer eliminated. The default for DG/UX, SVr4, and -Delta 88 SVr3.2 is to include this information; other 88k configurations -omit this information by default. +has had the frame pointer eliminated. The default for SVr4 and Delta 88 +SVr3.2 is to include this information; other 88k configurations omit this +information by default. @item -mocs-frame-position @opindex mocs-frame-position @@ -6522,7 +6290,7 @@ omit this information by default. When emitting COFF debugging information for automatic variables and parameters stored on the stack, use the offset from the canonical frame address, which is the stack pointer (register 31) on entry to the -function. The DG/UX, SVr4, Delta88 SVr3.2, and BCS configurations use +function. The SVr4 and Delta88 SVr3.2, and BCS configurations use @option{-mocs-frame-position}; other 88k configurations have the default @option{-mno-ocs-frame-position}. @@ -6609,9 +6377,8 @@ that is used on System V release 4. SVr4. @end enumerate -@option{-msvr4} is the default for the m88k-motorola-sysv4 and -m88k-dg-dgux m88k configurations. @option{-msvr3} is the default for all -other m88k configurations. +@option{-msvr4} is the default for the m88k-motorola-sysv4 configuration. +@option{-msvr3} is the default for all other m88k configurations. @item -mversion-03.00 @opindex mversion-03.00 @@ -8844,22 +8611,6 @@ Return VMS condition codes from main. The default is to return POSIX style condition (e.g.@ error) codes. @end table -@node Clipper Options -@subsection Clipper Options - -These @samp{-m} options are defined for the Clipper implementations: - -@table @gcctabopt -@item -mc300 -@opindex mc300 -Produce code for a C300 Clipper processor. This is the default. - -@item -mc400 -@opindex mc400 -Produce code for a C400 Clipper processor, i.e.@: use floating point -registers f8--f15. -@end table - @node H8/300 Options @subsection H8/300 Options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 34a38e6e6a7..14b911f82f6 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1376,60 +1376,6 @@ An item in the constant pool A symbol in the text segment of the current file @end table -@item AMD 29000 family---@file{a29k.h} -@table @code -@item l -Local register 0 - -@item b -Byte Pointer (@samp{BP}) register - -@item q -@samp{Q} register - -@item h -Special purpose register - -@item A -First accumulator register - -@item a -Other accumulator register - -@item f -Floating point register - -@item I -Constant greater than 0, less than 0x100 - -@item J -Constant greater than 0, less than 0x10000 - -@item K -Constant whose high 24 bits are on (1) - -@item L -16-bit constant whose high 8 bits are on (1) - -@item M -32-bit constant whose high 16 bits are on (1) - -@item N -32-bit negative constant that fits in 8 bits - -@item O -The constant 0x80000000 or, on the 29050, any 32-bit constant -whose low 16 bits are 0. - -@item P -16-bit negative constant that fits in 8 bits - -@item G -@itemx H -A floating point constant (in @code{asm} statements, use the machine -independent @samp{E} or @samp{F} instead) -@end table - @item AVR family---@file{avr.h} @table @code @item l @@ -2494,8 +2440,7 @@ Write the generated insn as a @code{parallel} with elements being a @code{set} of one register from the appropriate memory location (you may also need @code{use} or @code{clobber} elements). Use a @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See -@file{a29k.md} and @file{rs6000.md} for examples of the use of this insn -pattern. +@file{rs6000.md} for examples of the use of this insn pattern. @cindex @samp{store_multiple} instruction pattern @item @samp{store_multiple} diff --git a/gcc/doc/trouble.texi b/gcc/doc/trouble.texi index d6ba63259d6..a3ef96e2dfe 100644 --- a/gcc/doc/trouble.texi +++ b/gcc/doc/trouble.texi @@ -338,47 +338,6 @@ you cannot successfully use @samp{$} in identifiers on the RS/6000 due to a restriction in the IBM assembler. GAS supports these identifiers. -@item -@opindex mno-serialize-volatile -There is an assembler bug in versions of DG/UX prior to 5.4.2.01 that -occurs when the @samp{fldcr} instruction is used. GCC uses -@samp{fldcr} on the 88100 to serialize volatile memory references. Use -the option @option{-mno-serialize-volatile} if your version of the -assembler has this bug. - -@item -On VMS, GAS versions 1.38.1 and earlier may cause spurious warning -messages from the linker. These warning messages complain of mismatched -psect attributes. You can ignore them. - -@item -On NewsOS version 3, if you include both of the files @file{stddef.h} -and @file{sys/types.h}, you get an error because there are two typedefs -of @code{size_t}. You should change @file{sys/types.h} by adding these -lines around the definition of @code{size_t}: - -@smallexample -#ifndef _SIZE_T -#define _SIZE_T -@var{actual-typedef-here} -#endif -@end smallexample - -@cindex Alliant -@item -On the Alliant, the system's own convention for returning structures -and unions is unusual, and is not compatible with GCC no matter -what options are used. - -@cindex RT PC -@cindex IBM RT PC -@item -@opindex mhc-struct-return -On the IBM RT PC, the MetaWare HighC compiler (hc) uses a different -convention for structure and union returning. Use the option -@option{-mhc-struct-return} to tell GCC to use a convention compatible -with it. - @cindex VAX calling convention @cindex Ultrix calling convention @item @@ -394,43 +353,11 @@ these options to produce code compatible with the Fortran compiler: -fcall-saved-r2 -fcall-saved-r3 -fcall-saved-r4 -fcall-saved-r5 @end smallexample -@item -On the WE32k, you may find that programs compiled with GCC do not -work with the standard shared C library. You may need to link with -the ordinary C compiler. If you do so, you must specify the following -options: - -@smallexample --L/usr/local/lib/gcc-lib/we32k-att-sysv/2.8.1 -lgcc -lc_s -@end smallexample - -The first specifies where to find the library @file{libgcc.a} -specified with the @option{-lgcc} option. - -GCC does linking by invoking @command{ld}, just as @command{cc} does, and -there is no reason why it @emph{should} matter which compilation program -you use to invoke @command{ld}. If someone tracks this problem down, -it can probably be fixed easily. - @item On the Alpha, you may get assembler errors about invalid syntax as a result of floating point constants. This is due to a bug in the C library functions @code{ecvt}, @code{fcvt} and @code{gcvt}. Given valid floating point numbers, they sometimes print @samp{NaN}. - -@item -On Irix 4.0.5F (and perhaps in some other versions), an assembler bug -sometimes reorders instructions incorrectly when optimization is turned -on. If you think this may be happening to you, try using the GNU -assembler; GAS version 2.1 supports ECOFF on Irix. - -@opindex noasmopt -Or use the @option{-noasmopt} option when you compile GCC with itself, -and then again when you compile your program. (This is a temporary -kludge to turn off assembler optimization on Irix.) If this proves to -be what you need, edit the assembler spec in the file @file{specs} so -that it unconditionally passes @option{-O0} to the assembler, and never -passes @option{-O2} or @option{-O3}. @end itemize @node External Bugs -- 2.30.2