From c96d5e5a4a161b98cd6196a3f039825a8c5833d8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 12:57:00 +0000 Subject: [PATCH] ls180.il update --- .../non_generated/full_core_4_4ksram_ls180.il | 6458 +++++++++-------- 1 file changed, 3242 insertions(+), 3216 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index 27d000d..56e2e69 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -239066,293 +239066,293 @@ attribute \src "ls180.v:4.1-11017.10" attribute \cells_not_processed 1 module \ls180 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 attribute \src "ls180.v:10493.1-10497.4" - wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 attribute \src "ls180.v:10507.1-10511.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 attribute \src "ls180.v:10521.1-10525.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 attribute \src "ls180.v:10535.1-10539.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 attribute \src "ls180.v:10550.1-10554.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 attribute \src "ls180.v:10567.1-10571.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 attribute \src "ls180.v:10583.1-10587.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 attribute \src "ls180.v:10597.1-10601.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 attribute \src "ls180.v:3402.1-3495.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] attribute \src "ls180.v:7705.1-10349.4" @@ -239831,15 +239831,15 @@ module \ls180 wire $0\main_libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:204.12-204.74" + attribute \src "ls180.v:171.12-171.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:176.5-176.69" + attribute \src "ls180.v:175.5-175.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:181.5-181.72" + attribute \src "ls180.v:201.5-201.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:184.11-184.79" + attribute \src "ls180.v:204.11-204.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:188.12-188.78" + attribute \src "ls180.v:189.12-189.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -243078,95 +243078,95 @@ module \ls180 attribute \src "ls180.v:5758.77-5758.111" wire width 32 $add$ls180.v:5758$1161_Y attribute \src "ls180.v:7765.36-7765.70" - wire width 32 $add$ls180.v:7765$2602_Y + wire width 32 $add$ls180.v:7765$2604_Y attribute \src "ls180.v:7866.37-7866.72" - wire width 4 $add$ls180.v:7866$2635_Y + wire width 4 $add$ls180.v:7866$2637_Y attribute \src "ls180.v:7883.60-7883.119" - wire width 3 $add$ls180.v:7883$2639_Y + wire width 3 $add$ls180.v:7883$2641_Y attribute \src "ls180.v:7886.60-7886.119" - wire width 3 $add$ls180.v:7886$2640_Y + wire width 3 $add$ls180.v:7886$2642_Y attribute \src "ls180.v:7890.59-7890.116" - wire width 4 $add$ls180.v:7890$2645_Y + wire width 4 $add$ls180.v:7890$2647_Y attribute \src "ls180.v:7929.60-7929.119" - wire width 3 $add$ls180.v:7929$2655_Y + wire width 3 $add$ls180.v:7929$2657_Y attribute \src "ls180.v:7932.60-7932.119" - wire width 3 $add$ls180.v:7932$2656_Y + wire width 3 $add$ls180.v:7932$2658_Y attribute \src "ls180.v:7936.59-7936.116" - wire width 4 $add$ls180.v:7936$2661_Y + wire width 4 $add$ls180.v:7936$2663_Y attribute \src "ls180.v:7975.60-7975.119" - wire width 3 $add$ls180.v:7975$2671_Y + wire width 3 $add$ls180.v:7975$2673_Y attribute \src "ls180.v:7978.60-7978.119" - wire width 3 $add$ls180.v:7978$2672_Y + wire width 3 $add$ls180.v:7978$2674_Y attribute \src "ls180.v:7982.59-7982.116" - wire width 4 $add$ls180.v:7982$2677_Y + wire width 4 $add$ls180.v:7982$2679_Y attribute \src "ls180.v:8021.60-8021.119" - wire width 3 $add$ls180.v:8021$2687_Y + wire width 3 $add$ls180.v:8021$2689_Y attribute \src "ls180.v:8024.60-8024.119" - wire width 3 $add$ls180.v:8024$2688_Y + wire width 3 $add$ls180.v:8024$2690_Y attribute \src "ls180.v:8028.59-8028.116" - wire width 4 $add$ls180.v:8028$2693_Y + wire width 4 $add$ls180.v:8028$2695_Y attribute \src "ls180.v:8258.34-8258.66" - wire width 4 $add$ls180.v:8258$2747_Y + wire width 4 $add$ls180.v:8258$2749_Y attribute \src "ls180.v:8274.73-8274.131" - wire width 33 $add$ls180.v:8274$2750_Y + wire width 33 $add$ls180.v:8274$2752_Y attribute \src "ls180.v:8287.34-8287.66" - wire width 4 $add$ls180.v:8287$2754_Y + wire width 4 $add$ls180.v:8287$2756_Y attribute \src "ls180.v:8306.73-8306.131" - wire width 33 $add$ls180.v:8306$2757_Y + wire width 33 $add$ls180.v:8306$2759_Y attribute \src "ls180.v:8332.33-8332.65" - wire width 4 $add$ls180.v:8332$2765_Y + wire width 4 $add$ls180.v:8332$2767_Y attribute \src "ls180.v:8335.33-8335.65" - wire width 4 $add$ls180.v:8335$2766_Y + wire width 4 $add$ls180.v:8335$2768_Y attribute \src "ls180.v:8339.33-8339.64" - wire width 5 $add$ls180.v:8339$2771_Y + wire width 5 $add$ls180.v:8339$2773_Y attribute \src "ls180.v:8354.33-8354.65" - wire width 4 $add$ls180.v:8354$2776_Y + wire width 4 $add$ls180.v:8354$2778_Y attribute \src "ls180.v:8357.33-8357.65" - wire width 4 $add$ls180.v:8357$2777_Y + wire width 4 $add$ls180.v:8357$2779_Y attribute \src "ls180.v:8361.33-8361.64" - wire width 5 $add$ls180.v:8361$2782_Y + wire width 5 $add$ls180.v:8361$2784_Y attribute \src "ls180.v:8382.35-8382.70" - wire width 16 $add$ls180.v:8382$2784_Y + wire width 16 $add$ls180.v:8382$2786_Y attribute \src "ls180.v:8417.34-8417.68" - wire width 16 $add$ls180.v:8417$2789_Y + wire width 16 $add$ls180.v:8417$2791_Y attribute \src "ls180.v:8453.25-8453.49" - wire width 32 $add$ls180.v:8453$2794_Y + wire width 32 $add$ls180.v:8453$2796_Y attribute \src "ls180.v:8467.25-8467.49" - wire width 32 $add$ls180.v:8467$2798_Y + wire width 32 $add$ls180.v:8467$2800_Y attribute \src "ls180.v:8481.31-8481.61" - wire width 9 $add$ls180.v:8481$2803_Y + wire width 9 $add$ls180.v:8481$2805_Y attribute \src "ls180.v:8504.45-8504.88" - wire width 3 $add$ls180.v:8504$2807_Y + wire width 3 $add$ls180.v:8504$2809_Y attribute \src "ls180.v:8550.71-8550.114" - wire width 4 $add$ls180.v:8550$2813_Y + wire width 4 $add$ls180.v:8550$2815_Y attribute \src "ls180.v:8585.46-8585.90" - wire width 3 $add$ls180.v:8585$2819_Y + wire width 3 $add$ls180.v:8585$2821_Y attribute \src "ls180.v:8631.72-8631.116" - wire width 4 $add$ls180.v:8631$2825_Y + wire width 4 $add$ls180.v:8631$2827_Y attribute \src "ls180.v:8664.47-8664.92" - wire $add$ls180.v:8664$2831_Y + wire $add$ls180.v:8664$2833_Y attribute \src "ls180.v:8692.73-8692.118" - wire width 2 $add$ls180.v:8692$2837_Y + wire width 2 $add$ls180.v:8692$2839_Y attribute \src "ls180.v:8804.39-8804.75" - wire width 4 $add$ls180.v:8804$2850_Y + wire width 4 $add$ls180.v:8804$2852_Y attribute \src "ls180.v:8865.37-8865.73" - wire width 5 $add$ls180.v:8865$2854_Y + wire width 5 $add$ls180.v:8865$2856_Y attribute \src "ls180.v:8868.37-8868.73" - wire width 5 $add$ls180.v:8868$2855_Y + wire width 5 $add$ls180.v:8868$2857_Y attribute \src "ls180.v:8872.36-8872.70" - wire width 6 $add$ls180.v:8872$2860_Y + wire width 6 $add$ls180.v:8872$2862_Y attribute \src "ls180.v:8887.41-8887.80" - wire width 3 $add$ls180.v:8887$2864_Y + wire width 3 $add$ls180.v:8887$2866_Y attribute \src "ls180.v:8933.67-8933.106" - wire width 4 $add$ls180.v:8933$2870_Y + wire width 4 $add$ls180.v:8933$2872_Y attribute \src "ls180.v:8959.39-8959.76" - wire width 3 $add$ls180.v:8959$2872_Y + wire width 3 $add$ls180.v:8959$2874_Y attribute \src "ls180.v:8963.37-8963.73" - wire width 5 $add$ls180.v:8963$2876_Y + wire width 5 $add$ls180.v:8963$2878_Y attribute \src "ls180.v:8966.37-8966.73" - wire width 5 $add$ls180.v:8966$2877_Y + wire width 5 $add$ls180.v:8966$2879_Y attribute \src "ls180.v:8970.36-8970.70" - wire width 6 $add$ls180.v:8970$2882_Y + wire width 6 $add$ls180.v:8970$2884_Y attribute \src "ls180.v:2929.9-2929.90" wire $and$ls180.v:2929$53_Y attribute \src "ls180.v:2947.9-2947.90" @@ -245427,174 +245427,178 @@ module \ls180 wire $and$ls180.v:7468$2563_Y attribute \src "ls180.v:7468.38-7468.117" wire $and$ls180.v:7468$2564_Y + attribute \src "ls180.v:7687.18-7687.68" + wire $and$ls180.v:7687$2571_Y + attribute \src "ls180.v:7688.18-7688.68" + wire $and$ls180.v:7688$2572_Y attribute \src "ls180.v:7690.17-7690.67" - wire $and$ls180.v:7690$2572_Y + wire $and$ls180.v:7690$2574_Y attribute \src "ls180.v:7769.8-7769.67" - wire $and$ls180.v:7769$2603_Y - attribute \src "ls180.v:7769.7-7769.102" wire $and$ls180.v:7769$2605_Y + attribute \src "ls180.v:7769.7-7769.102" + wire $and$ls180.v:7769$2607_Y attribute \src "ls180.v:7788.7-7788.75" - wire $and$ls180.v:7788$2609_Y + wire $and$ls180.v:7788$2611_Y attribute \src "ls180.v:7792.8-7792.65" - wire $and$ls180.v:7792$2610_Y - attribute \src "ls180.v:7792.7-7792.99" wire $and$ls180.v:7792$2612_Y + attribute \src "ls180.v:7792.7-7792.99" + wire $and$ls180.v:7792$2614_Y attribute \src "ls180.v:7796.8-7796.65" - wire $and$ls180.v:7796$2613_Y - attribute \src "ls180.v:7796.7-7796.99" wire $and$ls180.v:7796$2615_Y + attribute \src "ls180.v:7796.7-7796.99" + wire $and$ls180.v:7796$2617_Y attribute \src "ls180.v:7800.8-7800.65" - wire $and$ls180.v:7800$2616_Y - attribute \src "ls180.v:7800.7-7800.99" wire $and$ls180.v:7800$2618_Y + attribute \src "ls180.v:7800.7-7800.99" + wire $and$ls180.v:7800$2620_Y attribute \src "ls180.v:7804.8-7804.65" - wire $and$ls180.v:7804$2619_Y - attribute \src "ls180.v:7804.7-7804.99" wire $and$ls180.v:7804$2621_Y + attribute \src "ls180.v:7804.7-7804.99" + wire $and$ls180.v:7804$2623_Y attribute \src "ls180.v:7812.7-7812.56" - wire $and$ls180.v:7812$2623_Y + wire $and$ls180.v:7812$2625_Y attribute \src "ls180.v:7840.7-7840.75" - wire $and$ls180.v:7840$2630_Y + wire $and$ls180.v:7840$2632_Y attribute \src "ls180.v:7882.8-7882.131" - wire $and$ls180.v:7882$2636_Y - attribute \src "ls180.v:7882.7-7882.190" wire $and$ls180.v:7882$2638_Y + attribute \src "ls180.v:7882.7-7882.190" + wire $and$ls180.v:7882$2640_Y attribute \src "ls180.v:7888.8-7888.131" - wire $and$ls180.v:7888$2641_Y - attribute \src "ls180.v:7888.7-7888.190" wire $and$ls180.v:7888$2643_Y + attribute \src "ls180.v:7888.7-7888.190" + wire $and$ls180.v:7888$2645_Y attribute \src "ls180.v:7928.8-7928.131" - wire $and$ls180.v:7928$2652_Y - attribute \src "ls180.v:7928.7-7928.190" wire $and$ls180.v:7928$2654_Y + attribute \src "ls180.v:7928.7-7928.190" + wire $and$ls180.v:7928$2656_Y attribute \src "ls180.v:7934.8-7934.131" - wire $and$ls180.v:7934$2657_Y - attribute \src "ls180.v:7934.7-7934.190" wire $and$ls180.v:7934$2659_Y + attribute \src "ls180.v:7934.7-7934.190" + wire $and$ls180.v:7934$2661_Y attribute \src "ls180.v:7974.8-7974.131" - wire $and$ls180.v:7974$2668_Y - attribute \src "ls180.v:7974.7-7974.190" wire $and$ls180.v:7974$2670_Y + attribute \src "ls180.v:7974.7-7974.190" + wire $and$ls180.v:7974$2672_Y attribute \src "ls180.v:7980.8-7980.131" - wire $and$ls180.v:7980$2673_Y - attribute \src "ls180.v:7980.7-7980.190" wire $and$ls180.v:7980$2675_Y + attribute \src "ls180.v:7980.7-7980.190" + wire $and$ls180.v:7980$2677_Y attribute \src "ls180.v:8020.8-8020.131" - wire $and$ls180.v:8020$2684_Y - attribute \src "ls180.v:8020.7-8020.190" wire $and$ls180.v:8020$2686_Y + attribute \src "ls180.v:8020.7-8020.190" + wire $and$ls180.v:8020$2688_Y attribute \src "ls180.v:8026.8-8026.131" - wire $and$ls180.v:8026$2689_Y - attribute \src "ls180.v:8026.7-8026.190" wire $and$ls180.v:8026$2691_Y + attribute \src "ls180.v:8026.7-8026.190" + wire $and$ls180.v:8026$2693_Y attribute \src "ls180.v:8223.48-8223.124" - wire $and$ls180.v:8223$2716_Y + wire $and$ls180.v:8223$2718_Y attribute \src "ls180.v:8223.130-8223.206" - wire $and$ls180.v:8223$2719_Y + wire $and$ls180.v:8223$2721_Y attribute \src "ls180.v:8223.212-8223.288" - wire $and$ls180.v:8223$2722_Y + wire $and$ls180.v:8223$2724_Y attribute \src "ls180.v:8223.294-8223.370" - wire $and$ls180.v:8223$2725_Y + wire $and$ls180.v:8223$2727_Y attribute \src "ls180.v:8224.49-8224.125" - wire $and$ls180.v:8224$2728_Y + wire $and$ls180.v:8224$2730_Y attribute \src "ls180.v:8224.131-8224.207" - wire $and$ls180.v:8224$2731_Y + wire $and$ls180.v:8224$2733_Y attribute \src "ls180.v:8224.213-8224.289" - wire $and$ls180.v:8224$2734_Y + wire $and$ls180.v:8224$2736_Y attribute \src "ls180.v:8224.295-8224.371" - wire $and$ls180.v:8224$2737_Y + wire $and$ls180.v:8224$2739_Y attribute \src "ls180.v:8243.8-8243.49" - wire $and$ls180.v:8243$2740_Y + wire $and$ls180.v:8243$2742_Y attribute \src "ls180.v:8246.8-8246.53" - wire $and$ls180.v:8246$2741_Y + wire $and$ls180.v:8246$2743_Y attribute \src "ls180.v:8251.8-8251.59" - wire $and$ls180.v:8251$2743_Y - attribute \src "ls180.v:8251.7-8251.90" wire $and$ls180.v:8251$2745_Y + attribute \src "ls180.v:8251.7-8251.90" + wire $and$ls180.v:8251$2747_Y attribute \src "ls180.v:8257.8-8257.59" - wire $and$ls180.v:8257$2746_Y + wire $and$ls180.v:8257$2748_Y attribute \src "ls180.v:8281.8-8281.48" - wire $and$ls180.v:8281$2753_Y + wire $and$ls180.v:8281$2755_Y attribute \src "ls180.v:8314.7-8314.57" - wire $and$ls180.v:8314$2759_Y + wire $and$ls180.v:8314$2761_Y attribute \src "ls180.v:8321.7-8321.57" - wire $and$ls180.v:8321$2761_Y + wire $and$ls180.v:8321$2763_Y attribute \src "ls180.v:8331.8-8331.75" - wire $and$ls180.v:8331$2762_Y - attribute \src "ls180.v:8331.7-8331.107" wire $and$ls180.v:8331$2764_Y + attribute \src "ls180.v:8331.7-8331.107" + wire $and$ls180.v:8331$2766_Y attribute \src "ls180.v:8337.8-8337.75" - wire $and$ls180.v:8337$2767_Y - attribute \src "ls180.v:8337.7-8337.107" wire $and$ls180.v:8337$2769_Y + attribute \src "ls180.v:8337.7-8337.107" + wire $and$ls180.v:8337$2771_Y attribute \src "ls180.v:8353.8-8353.75" - wire $and$ls180.v:8353$2773_Y - attribute \src "ls180.v:8353.7-8353.107" wire $and$ls180.v:8353$2775_Y + attribute \src "ls180.v:8353.7-8353.107" + wire $and$ls180.v:8353$2777_Y attribute \src "ls180.v:8359.8-8359.75" - wire $and$ls180.v:8359$2778_Y - attribute \src "ls180.v:8359.7-8359.107" wire $and$ls180.v:8359$2780_Y + attribute \src "ls180.v:8359.7-8359.107" + wire $and$ls180.v:8359$2782_Y attribute \src "ls180.v:8507.7-8507.96" - wire $and$ls180.v:8507$2808_Y + wire $and$ls180.v:8507$2810_Y attribute \src "ls180.v:8508.8-8508.93" - wire $and$ls180.v:8508$2809_Y + wire $and$ls180.v:8508$2811_Y attribute \src "ls180.v:8516.8-8516.93" - wire $and$ls180.v:8516$2810_Y + wire $and$ls180.v:8516$2812_Y attribute \src "ls180.v:8588.7-8588.98" - wire $and$ls180.v:8588$2820_Y + wire $and$ls180.v:8588$2822_Y attribute \src "ls180.v:8589.8-8589.95" - wire $and$ls180.v:8589$2821_Y + wire $and$ls180.v:8589$2823_Y attribute \src "ls180.v:8597.8-8597.95" - wire $and$ls180.v:8597$2822_Y + wire $and$ls180.v:8597$2824_Y attribute \src "ls180.v:8667.7-8667.100" - wire $and$ls180.v:8667$2832_Y + wire $and$ls180.v:8667$2834_Y attribute \src "ls180.v:8668.8-8668.97" - wire $and$ls180.v:8668$2833_Y + wire $and$ls180.v:8668$2835_Y attribute \src "ls180.v:8676.8-8676.97" - wire $and$ls180.v:8676$2834_Y + wire $and$ls180.v:8676$2836_Y attribute \src "ls180.v:8767.7-8767.82" - wire $and$ls180.v:8767$2840_Y + wire $and$ls180.v:8767$2842_Y attribute \src "ls180.v:8770.7-8770.82" - wire $and$ls180.v:8770$2841_Y + wire $and$ls180.v:8770$2843_Y attribute \src "ls180.v:8773.7-8773.82" - wire $and$ls180.v:8773$2842_Y + wire $and$ls180.v:8773$2844_Y attribute \src "ls180.v:8776.7-8776.82" - wire $and$ls180.v:8776$2843_Y + wire $and$ls180.v:8776$2845_Y attribute \src "ls180.v:8779.7-8779.82" - wire $and$ls180.v:8779$2844_Y + wire $and$ls180.v:8779$2846_Y attribute \src "ls180.v:8784.7-8784.82" - wire $and$ls180.v:8784$2845_Y + wire $and$ls180.v:8784$2847_Y attribute \src "ls180.v:8789.7-8789.82" - wire $and$ls180.v:8789$2846_Y + wire $and$ls180.v:8789$2848_Y attribute \src "ls180.v:8794.7-8794.82" - wire $and$ls180.v:8794$2847_Y + wire $and$ls180.v:8794$2849_Y attribute \src "ls180.v:8799.7-8799.82" - wire $and$ls180.v:8799$2848_Y + wire $and$ls180.v:8799$2850_Y attribute \src "ls180.v:8864.8-8864.83" - wire $and$ls180.v:8864$2851_Y - attribute \src "ls180.v:8864.7-8864.119" wire $and$ls180.v:8864$2853_Y + attribute \src "ls180.v:8864.7-8864.119" + wire $and$ls180.v:8864$2855_Y attribute \src "ls180.v:8870.8-8870.83" - wire $and$ls180.v:8870$2856_Y - attribute \src "ls180.v:8870.7-8870.119" wire $and$ls180.v:8870$2858_Y + attribute \src "ls180.v:8870.7-8870.119" + wire $and$ls180.v:8870$2860_Y attribute \src "ls180.v:8890.7-8890.88" - wire $and$ls180.v:8890$2865_Y + wire $and$ls180.v:8890$2867_Y attribute \src "ls180.v:8891.8-8891.85" - wire $and$ls180.v:8891$2866_Y + wire $and$ls180.v:8891$2868_Y attribute \src "ls180.v:8899.8-8899.85" - wire $and$ls180.v:8899$2867_Y + wire $and$ls180.v:8899$2869_Y attribute \src "ls180.v:8955.7-8955.88" - wire $and$ls180.v:8955$2871_Y + wire $and$ls180.v:8955$2873_Y attribute \src "ls180.v:8962.8-8962.83" - wire $and$ls180.v:8962$2873_Y - attribute \src "ls180.v:8962.7-8962.119" wire $and$ls180.v:8962$2875_Y + attribute \src "ls180.v:8962.7-8962.119" + wire $and$ls180.v:8962$2877_Y attribute \src "ls180.v:8968.8-8968.83" - wire $and$ls180.v:8968$2878_Y - attribute \src "ls180.v:8968.7-8968.119" wire $and$ls180.v:8968$2880_Y + attribute \src "ls180.v:8968.7-8968.119" + wire $and$ls180.v:8968$2882_Y attribute \src "ls180.v:2930.30-2930.76" wire $eq$ls180.v:2930$54_Y attribute \src "ls180.v:2937.11-2937.42" @@ -246608,115 +246612,115 @@ module \ls180 attribute \src "ls180.v:7189.294-7189.327" wire $eq$ls180.v:7189$2514_Y attribute \src "ls180.v:7773.8-7773.38" - wire $eq$ls180.v:7773$2606_Y + wire $eq$ls180.v:7773$2608_Y attribute \src "ls180.v:7820.8-7820.42" - wire $eq$ls180.v:7820$2626_Y + wire $eq$ls180.v:7820$2628_Y attribute \src "ls180.v:7840.38-7840.74" - wire $eq$ls180.v:7840$2629_Y + wire $eq$ls180.v:7840$2631_Y attribute \src "ls180.v:7847.7-7847.43" - wire $eq$ls180.v:7847$2631_Y + wire $eq$ls180.v:7847$2633_Y attribute \src "ls180.v:7854.7-7854.43" - wire $eq$ls180.v:7854$2632_Y + wire $eq$ls180.v:7854$2634_Y attribute \src "ls180.v:7862.7-7862.43" - wire $eq$ls180.v:7862$2633_Y + wire $eq$ls180.v:7862$2635_Y attribute \src "ls180.v:7914.9-7914.54" - wire $eq$ls180.v:7914$2651_Y + wire $eq$ls180.v:7914$2653_Y attribute \src "ls180.v:7960.9-7960.54" - wire $eq$ls180.v:7960$2667_Y + wire $eq$ls180.v:7960$2669_Y attribute \src "ls180.v:8006.9-8006.54" - wire $eq$ls180.v:8006$2683_Y + wire $eq$ls180.v:8006$2685_Y attribute \src "ls180.v:8052.9-8052.54" - wire $eq$ls180.v:8052$2699_Y + wire $eq$ls180.v:8052$2701_Y attribute \src "ls180.v:8202.9-8202.41" - wire $eq$ls180.v:8202$2711_Y + wire $eq$ls180.v:8202$2713_Y attribute \src "ls180.v:8217.9-8217.41" - wire $eq$ls180.v:8217$2714_Y + wire $eq$ls180.v:8217$2716_Y attribute \src "ls180.v:8223.49-8223.82" - wire $eq$ls180.v:8223$2715_Y + wire $eq$ls180.v:8223$2717_Y attribute \src "ls180.v:8223.131-8223.164" - wire $eq$ls180.v:8223$2718_Y + wire $eq$ls180.v:8223$2720_Y attribute \src "ls180.v:8223.213-8223.246" - wire $eq$ls180.v:8223$2721_Y + wire $eq$ls180.v:8223$2723_Y attribute \src "ls180.v:8223.295-8223.328" - wire $eq$ls180.v:8223$2724_Y + wire $eq$ls180.v:8223$2726_Y attribute \src "ls180.v:8224.50-8224.83" - wire $eq$ls180.v:8224$2727_Y + wire $eq$ls180.v:8224$2729_Y attribute \src "ls180.v:8224.132-8224.165" - wire $eq$ls180.v:8224$2730_Y + wire $eq$ls180.v:8224$2732_Y attribute \src "ls180.v:8224.214-8224.247" - wire $eq$ls180.v:8224$2733_Y + wire $eq$ls180.v:8224$2735_Y attribute \src "ls180.v:8224.296-8224.329" - wire $eq$ls180.v:8224$2736_Y + wire $eq$ls180.v:8224$2738_Y attribute \src "ls180.v:8259.9-8259.42" - wire $eq$ls180.v:8259$2748_Y + wire $eq$ls180.v:8259$2750_Y attribute \src "ls180.v:8262.10-8262.43" - wire $eq$ls180.v:8262$2749_Y + wire $eq$ls180.v:8262$2751_Y attribute \src "ls180.v:8288.9-8288.42" - wire $eq$ls180.v:8288$2755_Y + wire $eq$ls180.v:8288$2757_Y attribute \src "ls180.v:8293.10-8293.43" - wire $eq$ls180.v:8293$2756_Y + wire $eq$ls180.v:8293$2758_Y attribute \src "ls180.v:8500.9-8500.53" - wire $eq$ls180.v:8500$2805_Y + wire $eq$ls180.v:8500$2807_Y attribute \src "ls180.v:8581.9-8581.54" - wire $eq$ls180.v:8581$2817_Y + wire $eq$ls180.v:8581$2819_Y attribute \src "ls180.v:8660.9-8660.55" - wire $eq$ls180.v:8660$2829_Y + wire $eq$ls180.v:8660$2831_Y attribute \src "ls180.v:8883.9-8883.49" - wire $eq$ls180.v:8883$2862_Y + wire $eq$ls180.v:8883$2864_Y attribute \src "ls180.v:8459.8-8459.54" - wire $ge$ls180.v:8459$2797_Y + wire $ge$ls180.v:8459$2799_Y attribute \src "ls180.v:8473.8-8473.54" - wire $ge$ls180.v:8473$2801_Y + wire $ge$ls180.v:8473$2803_Y attribute \src "ls180.v:5342.47-5342.83" wire $gt$ls180.v:5342$1064_Y attribute \src "ls180.v:5348.7-5348.43" wire $lt$ls180.v:5348$1067_Y attribute \src "ls180.v:8454.8-8454.43" - wire $lt$ls180.v:8454$2795_Y + wire $lt$ls180.v:8454$2797_Y attribute \src "ls180.v:8468.8-8468.43" - wire $lt$ls180.v:8468$2799_Y + wire $lt$ls180.v:8468$2801_Y attribute \src "ls180.v:10373.33-10373.36" - wire width 64 $memrd$\mem$ls180.v:10373$2916_DATA + wire width 64 $memrd$\mem$ls180.v:10373$2918_DATA attribute \src "ls180.v:10401.27-10401.32" - wire width 64 $memrd$\mem_1$ls180.v:10401$2942_DATA + wire width 64 $memrd$\mem_1$ls180.v:10401$2944_DATA attribute \src "ls180.v:10429.27-10429.32" - wire width 64 $memrd$\mem_2$ls180.v:10429$2968_DATA + wire width 64 $memrd$\mem_2$ls180.v:10429$2970_DATA attribute \src "ls180.v:10457.27-10457.32" - wire width 64 $memrd$\mem_3$ls180.v:10457$2994_DATA + wire width 64 $memrd$\mem_3$ls180.v:10457$2996_DATA attribute \src "ls180.v:10485.27-10485.32" - wire width 64 $memrd$\mem_4$ls180.v:10485$3020_DATA + wire width 64 $memrd$\mem_4$ls180.v:10485$3022_DATA attribute \src "ls180.v:10496.12-10496.19" - wire width 25 $memrd$\storage$ls180.v:10496$3025_DATA + wire width 25 $memrd$\storage$ls180.v:10496$3027_DATA attribute \src "ls180.v:10503.68-10503.75" - wire width 25 $memrd$\storage$ls180.v:10503$3027_DATA + wire width 25 $memrd$\storage$ls180.v:10503$3029_DATA attribute \src "ls180.v:10510.14-10510.23" - wire width 25 $memrd$\storage_1$ls180.v:10510$3032_DATA + wire width 25 $memrd$\storage_1$ls180.v:10510$3034_DATA attribute \src "ls180.v:10517.68-10517.77" - wire width 25 $memrd$\storage_1$ls180.v:10517$3034_DATA + wire width 25 $memrd$\storage_1$ls180.v:10517$3036_DATA attribute \src "ls180.v:10524.14-10524.23" - wire width 25 $memrd$\storage_2$ls180.v:10524$3039_DATA + wire width 25 $memrd$\storage_2$ls180.v:10524$3041_DATA attribute \src "ls180.v:10531.68-10531.77" - wire width 25 $memrd$\storage_2$ls180.v:10531$3041_DATA + wire width 25 $memrd$\storage_2$ls180.v:10531$3043_DATA attribute \src "ls180.v:10538.14-10538.23" - wire width 25 $memrd$\storage_3$ls180.v:10538$3046_DATA + wire width 25 $memrd$\storage_3$ls180.v:10538$3048_DATA attribute \src "ls180.v:10545.68-10545.77" - wire width 25 $memrd$\storage_3$ls180.v:10545$3048_DATA + wire width 25 $memrd$\storage_3$ls180.v:10545$3050_DATA attribute \src "ls180.v:10553.14-10553.23" - wire width 10 $memrd$\storage_4$ls180.v:10553$3053_DATA + wire width 10 $memrd$\storage_4$ls180.v:10553$3055_DATA attribute \src "ls180.v:10558.15-10558.24" - wire width 10 $memrd$\storage_4$ls180.v:10558$3055_DATA + wire width 10 $memrd$\storage_4$ls180.v:10558$3057_DATA attribute \src "ls180.v:10570.14-10570.23" - wire width 10 $memrd$\storage_5$ls180.v:10570$3060_DATA + wire width 10 $memrd$\storage_5$ls180.v:10570$3062_DATA attribute \src "ls180.v:10575.15-10575.24" - wire width 10 $memrd$\storage_5$ls180.v:10575$3062_DATA + wire width 10 $memrd$\storage_5$ls180.v:10575$3064_DATA attribute \src "ls180.v:10586.14-10586.23" - wire width 10 $memrd$\storage_6$ls180.v:10586$3067_DATA + wire width 10 $memrd$\storage_6$ls180.v:10586$3069_DATA attribute \src "ls180.v:10593.45-10593.54" - wire width 10 $memrd$\storage_6$ls180.v:10593$3069_DATA + wire width 10 $memrd$\storage_6$ls180.v:10593$3071_DATA attribute \src "ls180.v:10600.14-10600.23" - wire width 10 $memrd$\storage_7$ls180.v:10600$3074_DATA + wire width 10 $memrd$\storage_7$ls180.v:10600$3076_DATA attribute \src "ls180.v:10607.45-10607.54" - wire width 10 $memrd$\storage_7$ls180.v:10607$3076_DATA + wire width 10 $memrd$\storage_7$ls180.v:10607$3078_DATA attribute \src "ls180.v:0.0-0.0" wire width 6 $memwr$\mem$ls180.v:10355$1_ADDR attribute \src "ls180.v:0.0-0.0" @@ -247056,13 +247060,13 @@ module \ls180 attribute \src "ls180.v:5878.79-5878.119" wire $ne$ls180.v:5878$1177_Y attribute \src "ls180.v:7763.7-7763.52" - wire $ne$ls180.v:7763$2601_Y + wire $ne$ls180.v:7763$2603_Y attribute \src "ls180.v:7829.9-7829.43" - wire $ne$ls180.v:7829$2627_Y + wire $ne$ls180.v:7829$2629_Y attribute \src "ls180.v:7865.8-7865.44" - wire $ne$ls180.v:7865$2634_Y + wire $ne$ls180.v:7865$2636_Y attribute \src "ls180.v:8803.9-8803.47" - wire $ne$ls180.v:8803$2849_Y + wire $ne$ls180.v:8803$2851_Y attribute \src "ls180.v:2893.33-2893.73" wire $not$ls180.v:2893$50_Y attribute \src "ls180.v:2932.48-2932.69" @@ -247608,145 +247612,145 @@ module \ls180 attribute \src "ls180.v:7189.86-7189.330" wire $not$ls180.v:7189$2517_Y attribute \src "ls180.v:7690.18-7690.42" - wire $not$ls180.v:7690$2571_Y + wire $not$ls180.v:7690$2573_Y attribute \src "ls180.v:7769.72-7769.101" - wire $not$ls180.v:7769$2604_Y + wire $not$ls180.v:7769$2606_Y attribute \src "ls180.v:7788.8-7788.38" - wire $not$ls180.v:7788$2608_Y + wire $not$ls180.v:7788$2610_Y attribute \src "ls180.v:7792.70-7792.98" - wire $not$ls180.v:7792$2611_Y + wire $not$ls180.v:7792$2613_Y attribute \src "ls180.v:7796.70-7796.98" - wire $not$ls180.v:7796$2614_Y + wire $not$ls180.v:7796$2616_Y attribute \src "ls180.v:7800.70-7800.98" - wire $not$ls180.v:7800$2617_Y + wire $not$ls180.v:7800$2619_Y attribute \src "ls180.v:7804.70-7804.98" - wire $not$ls180.v:7804$2620_Y + wire $not$ls180.v:7804$2622_Y attribute \src "ls180.v:7812.32-7812.55" - wire $not$ls180.v:7812$2622_Y + wire $not$ls180.v:7812$2624_Y attribute \src "ls180.v:7882.136-7882.189" - wire $not$ls180.v:7882$2637_Y + wire $not$ls180.v:7882$2639_Y attribute \src "ls180.v:7888.136-7888.189" - wire $not$ls180.v:7888$2642_Y + wire $not$ls180.v:7888$2644_Y attribute \src "ls180.v:7889.8-7889.61" - wire $not$ls180.v:7889$2644_Y + wire $not$ls180.v:7889$2646_Y attribute \src "ls180.v:7897.8-7897.56" - wire $not$ls180.v:7897$2647_Y + wire $not$ls180.v:7897$2649_Y attribute \src "ls180.v:7912.8-7912.46" - wire $not$ls180.v:7912$2649_Y + wire $not$ls180.v:7912$2651_Y attribute \src "ls180.v:7928.136-7928.189" - wire $not$ls180.v:7928$2653_Y + wire $not$ls180.v:7928$2655_Y attribute \src "ls180.v:7934.136-7934.189" - wire $not$ls180.v:7934$2658_Y + wire $not$ls180.v:7934$2660_Y attribute \src "ls180.v:7935.8-7935.61" - wire $not$ls180.v:7935$2660_Y + wire $not$ls180.v:7935$2662_Y attribute \src "ls180.v:7943.8-7943.56" - wire $not$ls180.v:7943$2663_Y + wire $not$ls180.v:7943$2665_Y attribute \src "ls180.v:7958.8-7958.46" - wire $not$ls180.v:7958$2665_Y + wire $not$ls180.v:7958$2667_Y attribute \src "ls180.v:7974.136-7974.189" - wire $not$ls180.v:7974$2669_Y + wire $not$ls180.v:7974$2671_Y attribute \src "ls180.v:7980.136-7980.189" - wire $not$ls180.v:7980$2674_Y + wire $not$ls180.v:7980$2676_Y attribute \src "ls180.v:7981.8-7981.61" - wire $not$ls180.v:7981$2676_Y + wire $not$ls180.v:7981$2678_Y attribute \src "ls180.v:7989.8-7989.56" - wire $not$ls180.v:7989$2679_Y + wire $not$ls180.v:7989$2681_Y attribute \src "ls180.v:8004.8-8004.46" - wire $not$ls180.v:8004$2681_Y + wire $not$ls180.v:8004$2683_Y attribute \src "ls180.v:8020.136-8020.189" - wire $not$ls180.v:8020$2685_Y + wire $not$ls180.v:8020$2687_Y attribute \src "ls180.v:8026.136-8026.189" - wire $not$ls180.v:8026$2690_Y + wire $not$ls180.v:8026$2692_Y attribute \src "ls180.v:8027.8-8027.61" - wire $not$ls180.v:8027$2692_Y + wire $not$ls180.v:8027$2694_Y attribute \src "ls180.v:8035.8-8035.56" - wire $not$ls180.v:8035$2695_Y + wire $not$ls180.v:8035$2697_Y attribute \src "ls180.v:8050.8-8050.46" - wire $not$ls180.v:8050$2697_Y + wire $not$ls180.v:8050$2699_Y attribute \src "ls180.v:8058.7-8058.22" - wire $not$ls180.v:8058$2700_Y + wire $not$ls180.v:8058$2702_Y attribute \src "ls180.v:8061.8-8061.29" - wire $not$ls180.v:8061$2701_Y + wire $not$ls180.v:8061$2703_Y attribute \src "ls180.v:8065.7-8065.22" - wire $not$ls180.v:8065$2703_Y + wire $not$ls180.v:8065$2705_Y attribute \src "ls180.v:8068.8-8068.29" - wire $not$ls180.v:8068$2704_Y + wire $not$ls180.v:8068$2706_Y attribute \src "ls180.v:8187.30-8187.60" - wire $not$ls180.v:8187$2706_Y + wire $not$ls180.v:8187$2708_Y attribute \src "ls180.v:8188.30-8188.60" - wire $not$ls180.v:8188$2707_Y + wire $not$ls180.v:8188$2709_Y attribute \src "ls180.v:8189.29-8189.59" - wire $not$ls180.v:8189$2708_Y + wire $not$ls180.v:8189$2710_Y attribute \src "ls180.v:8200.8-8200.33" - wire $not$ls180.v:8200$2709_Y + wire $not$ls180.v:8200$2711_Y attribute \src "ls180.v:8215.8-8215.33" - wire $not$ls180.v:8215$2712_Y + wire $not$ls180.v:8215$2714_Y attribute \src "ls180.v:8251.36-8251.58" - wire $not$ls180.v:8251$2742_Y - attribute \src "ls180.v:8251.64-8251.89" wire $not$ls180.v:8251$2744_Y + attribute \src "ls180.v:8251.64-8251.89" + wire $not$ls180.v:8251$2746_Y attribute \src "ls180.v:8280.7-8280.29" - wire $not$ls180.v:8280$2751_Y + wire $not$ls180.v:8280$2753_Y attribute \src "ls180.v:8281.9-8281.26" - wire $not$ls180.v:8281$2752_Y + wire $not$ls180.v:8281$2754_Y attribute \src "ls180.v:8314.8-8314.29" - wire $not$ls180.v:8314$2758_Y + wire $not$ls180.v:8314$2760_Y attribute \src "ls180.v:8321.8-8321.29" - wire $not$ls180.v:8321$2760_Y + wire $not$ls180.v:8321$2762_Y attribute \src "ls180.v:8331.80-8331.106" - wire $not$ls180.v:8331$2763_Y + wire $not$ls180.v:8331$2765_Y attribute \src "ls180.v:8337.80-8337.106" - wire $not$ls180.v:8337$2768_Y + wire $not$ls180.v:8337$2770_Y attribute \src "ls180.v:8338.8-8338.34" - wire $not$ls180.v:8338$2770_Y + wire $not$ls180.v:8338$2772_Y attribute \src "ls180.v:8353.80-8353.106" - wire $not$ls180.v:8353$2774_Y + wire $not$ls180.v:8353$2776_Y attribute \src "ls180.v:8359.80-8359.106" - wire $not$ls180.v:8359$2779_Y + wire $not$ls180.v:8359$2781_Y attribute \src "ls180.v:8360.8-8360.34" - wire $not$ls180.v:8360$2781_Y + wire $not$ls180.v:8360$2783_Y attribute \src "ls180.v:8391.22-8391.41" - wire $not$ls180.v:8391$2785_Y + wire $not$ls180.v:8391$2787_Y attribute \src "ls180.v:8391.46-8391.73" - wire $not$ls180.v:8391$2786_Y + wire $not$ls180.v:8391$2788_Y attribute \src "ls180.v:8426.22-8426.40" - wire $not$ls180.v:8426$2790_Y + wire $not$ls180.v:8426$2792_Y attribute \src "ls180.v:8426.45-8426.70" - wire $not$ls180.v:8426$2791_Y + wire $not$ls180.v:8426$2793_Y attribute \src "ls180.v:8480.7-8480.31" - wire $not$ls180.v:8480$2802_Y + wire $not$ls180.v:8480$2804_Y attribute \src "ls180.v:8552.8-8552.46" - wire $not$ls180.v:8552$2814_Y + wire $not$ls180.v:8552$2816_Y attribute \src "ls180.v:8633.8-8633.47" - wire $not$ls180.v:8633$2826_Y + wire $not$ls180.v:8633$2828_Y attribute \src "ls180.v:8694.8-8694.48" - wire $not$ls180.v:8694$2838_Y + wire $not$ls180.v:8694$2840_Y attribute \src "ls180.v:8864.88-8864.118" - wire $not$ls180.v:8864$2852_Y + wire $not$ls180.v:8864$2854_Y attribute \src "ls180.v:8870.88-8870.118" - wire $not$ls180.v:8870$2857_Y + wire $not$ls180.v:8870$2859_Y attribute \src "ls180.v:8871.8-8871.38" - wire $not$ls180.v:8871$2859_Y + wire $not$ls180.v:8871$2861_Y attribute \src "ls180.v:8962.88-8962.118" - wire $not$ls180.v:8962$2874_Y + wire $not$ls180.v:8962$2876_Y attribute \src "ls180.v:8968.88-8968.118" - wire $not$ls180.v:8968$2879_Y + wire $not$ls180.v:8968$2881_Y attribute \src "ls180.v:8969.8-8969.38" - wire $not$ls180.v:8969$2881_Y + wire $not$ls180.v:8969$2883_Y attribute \src "ls180.v:8989.9-8989.28" - wire $not$ls180.v:8989$2884_Y + wire $not$ls180.v:8989$2886_Y attribute \src "ls180.v:9008.9-9008.28" - wire $not$ls180.v:9008$2885_Y + wire $not$ls180.v:9008$2887_Y attribute \src "ls180.v:9027.9-9027.28" - wire $not$ls180.v:9027$2886_Y + wire $not$ls180.v:9027$2888_Y attribute \src "ls180.v:9046.9-9046.28" - wire $not$ls180.v:9046$2887_Y + wire $not$ls180.v:9046$2889_Y attribute \src "ls180.v:9065.9-9065.28" - wire $not$ls180.v:9065$2888_Y + wire $not$ls180.v:9065$2890_Y attribute \src "ls180.v:9086.8-9086.21" - wire $not$ls180.v:9086$2889_Y + wire $not$ls180.v:9086$2891_Y attribute \src "ls180.v:10709.8-10709.51" - wire $or$ls180.v:10709$3077_Y + wire $or$ls180.v:10709$3079_Y attribute \src "ls180.v:2934.10-2934.71" wire $or$ls180.v:2934$57_Y attribute \src "ls180.v:2994.10-2994.71" @@ -248120,125 +248124,125 @@ module \ls180 attribute \src "ls180.v:7189.88-7189.329" wire $or$ls180.v:7189$2516_Y attribute \src "ls180.v:7706.20-7706.71" - wire $or$ls180.v:7706$2574_Y + wire $or$ls180.v:7706$2576_Y attribute \src "ls180.v:7707.20-7707.71" - wire $or$ls180.v:7707$2575_Y + wire $or$ls180.v:7707$2577_Y attribute \src "ls180.v:7708.20-7708.71" - wire $or$ls180.v:7708$2576_Y + wire $or$ls180.v:7708$2578_Y attribute \src "ls180.v:7709.20-7709.71" - wire $or$ls180.v:7709$2577_Y + wire $or$ls180.v:7709$2579_Y attribute \src "ls180.v:7710.20-7710.71" - wire $or$ls180.v:7710$2578_Y + wire $or$ls180.v:7710$2580_Y attribute \src "ls180.v:7711.20-7711.71" - wire $or$ls180.v:7711$2579_Y + wire $or$ls180.v:7711$2581_Y attribute \src "ls180.v:7712.20-7712.71" - wire $or$ls180.v:7712$2580_Y + wire $or$ls180.v:7712$2582_Y attribute \src "ls180.v:7713.20-7713.71" - wire $or$ls180.v:7713$2581_Y + wire $or$ls180.v:7713$2583_Y attribute \src "ls180.v:7714.20-7714.71" - wire $or$ls180.v:7714$2582_Y + wire $or$ls180.v:7714$2584_Y attribute \src "ls180.v:7715.20-7715.71" - wire $or$ls180.v:7715$2583_Y + wire $or$ls180.v:7715$2585_Y attribute \src "ls180.v:7716.21-7716.73" - wire $or$ls180.v:7716$2584_Y + wire $or$ls180.v:7716$2586_Y attribute \src "ls180.v:7717.21-7717.73" - wire $or$ls180.v:7717$2585_Y + wire $or$ls180.v:7717$2587_Y attribute \src "ls180.v:7718.21-7718.73" - wire $or$ls180.v:7718$2586_Y + wire $or$ls180.v:7718$2588_Y attribute \src "ls180.v:7719.21-7719.73" - wire $or$ls180.v:7719$2587_Y + wire $or$ls180.v:7719$2589_Y attribute \src "ls180.v:7720.21-7720.73" - wire $or$ls180.v:7720$2588_Y + wire $or$ls180.v:7720$2590_Y attribute \src "ls180.v:7721.21-7721.73" - wire $or$ls180.v:7721$2589_Y + wire $or$ls180.v:7721$2591_Y attribute \src "ls180.v:7722.21-7722.73" - wire $or$ls180.v:7722$2590_Y + wire $or$ls180.v:7722$2592_Y attribute \src "ls180.v:7723.21-7723.73" - wire $or$ls180.v:7723$2591_Y + wire $or$ls180.v:7723$2593_Y attribute \src "ls180.v:7724.21-7724.73" - wire $or$ls180.v:7724$2592_Y + wire $or$ls180.v:7724$2594_Y attribute \src "ls180.v:7725.21-7725.73" - wire $or$ls180.v:7725$2593_Y + wire $or$ls180.v:7725$2595_Y attribute \src "ls180.v:7726.21-7726.73" - wire $or$ls180.v:7726$2594_Y + wire $or$ls180.v:7726$2596_Y attribute \src "ls180.v:7727.21-7727.73" - wire $or$ls180.v:7727$2595_Y + wire $or$ls180.v:7727$2597_Y attribute \src "ls180.v:7728.21-7728.73" - wire $or$ls180.v:7728$2596_Y + wire $or$ls180.v:7728$2598_Y attribute \src "ls180.v:7729.21-7729.73" - wire $or$ls180.v:7729$2597_Y + wire $or$ls180.v:7729$2599_Y attribute \src "ls180.v:7730.7-7730.68" - wire $or$ls180.v:7730$2598_Y + wire $or$ls180.v:7730$2600_Y attribute \src "ls180.v:7741.7-7741.68" - wire $or$ls180.v:7741$2599_Y + wire $or$ls180.v:7741$2601_Y attribute \src "ls180.v:7752.7-7752.50" - wire $or$ls180.v:7752$2600_Y + wire $or$ls180.v:7752$2602_Y attribute \src "ls180.v:7897.7-7897.107" - wire $or$ls180.v:7897$2648_Y + wire $or$ls180.v:7897$2650_Y attribute \src "ls180.v:7943.7-7943.107" - wire $or$ls180.v:7943$2664_Y + wire $or$ls180.v:7943$2666_Y attribute \src "ls180.v:7989.7-7989.107" - wire $or$ls180.v:7989$2680_Y + wire $or$ls180.v:7989$2682_Y attribute \src "ls180.v:8035.7-8035.107" - wire $or$ls180.v:8035$2696_Y + wire $or$ls180.v:8035$2698_Y attribute \src "ls180.v:8223.40-8223.125" - wire $or$ls180.v:8223$2717_Y + wire $or$ls180.v:8223$2719_Y attribute \src "ls180.v:8223.39-8223.207" - wire $or$ls180.v:8223$2720_Y + wire $or$ls180.v:8223$2722_Y attribute \src "ls180.v:8223.38-8223.289" - wire $or$ls180.v:8223$2723_Y + wire $or$ls180.v:8223$2725_Y attribute \src "ls180.v:8223.37-8223.371" - wire $or$ls180.v:8223$2726_Y + wire $or$ls180.v:8223$2728_Y attribute \src "ls180.v:8224.41-8224.126" - wire $or$ls180.v:8224$2729_Y + wire $or$ls180.v:8224$2731_Y attribute \src "ls180.v:8224.40-8224.208" - wire $or$ls180.v:8224$2732_Y + wire $or$ls180.v:8224$2734_Y attribute \src "ls180.v:8224.39-8224.290" - wire $or$ls180.v:8224$2735_Y + wire $or$ls180.v:8224$2737_Y attribute \src "ls180.v:8224.38-8224.372" - wire $or$ls180.v:8224$2738_Y + wire $or$ls180.v:8224$2740_Y attribute \src "ls180.v:8228.7-8228.49" - wire $or$ls180.v:8228$2739_Y + wire $or$ls180.v:8228$2741_Y attribute \src "ls180.v:8391.21-8391.74" - wire $or$ls180.v:8391$2787_Y + wire $or$ls180.v:8391$2789_Y attribute \src "ls180.v:8426.21-8426.71" - wire $or$ls180.v:8426$2792_Y + wire $or$ls180.v:8426$2794_Y attribute \src "ls180.v:8494.32-8494.85" - wire $or$ls180.v:8494$2804_Y + wire $or$ls180.v:8494$2806_Y attribute \src "ls180.v:8500.8-8500.97" - wire $or$ls180.v:8500$2806_Y + wire $or$ls180.v:8500$2808_Y attribute \src "ls180.v:8517.52-8517.139" - wire $or$ls180.v:8517$2811_Y + wire $or$ls180.v:8517$2813_Y attribute \src "ls180.v:8518.51-8518.136" - wire $or$ls180.v:8518$2812_Y + wire $or$ls180.v:8518$2814_Y attribute \src "ls180.v:8552.7-8552.87" - wire $or$ls180.v:8552$2815_Y + wire $or$ls180.v:8552$2817_Y attribute \src "ls180.v:8575.33-8575.88" - wire $or$ls180.v:8575$2816_Y + wire $or$ls180.v:8575$2818_Y attribute \src "ls180.v:8581.8-8581.99" - wire $or$ls180.v:8581$2818_Y + wire $or$ls180.v:8581$2820_Y attribute \src "ls180.v:8598.53-8598.142" - wire $or$ls180.v:8598$2823_Y + wire $or$ls180.v:8598$2825_Y attribute \src "ls180.v:8599.52-8599.139" - wire $or$ls180.v:8599$2824_Y + wire $or$ls180.v:8599$2826_Y attribute \src "ls180.v:8633.7-8633.89" - wire $or$ls180.v:8633$2827_Y + wire $or$ls180.v:8633$2829_Y attribute \src "ls180.v:8654.34-8654.91" - wire $or$ls180.v:8654$2828_Y + wire $or$ls180.v:8654$2830_Y attribute \src "ls180.v:8660.8-8660.101" - wire $or$ls180.v:8660$2830_Y + wire $or$ls180.v:8660$2832_Y attribute \src "ls180.v:8677.54-8677.145" - wire $or$ls180.v:8677$2835_Y + wire $or$ls180.v:8677$2837_Y attribute \src "ls180.v:8678.53-8678.142" - wire $or$ls180.v:8678$2836_Y + wire $or$ls180.v:8678$2838_Y attribute \src "ls180.v:8694.7-8694.91" - wire $or$ls180.v:8694$2839_Y + wire $or$ls180.v:8694$2841_Y attribute \src "ls180.v:8883.8-8883.89" - wire $or$ls180.v:8883$2863_Y + wire $or$ls180.v:8883$2865_Y attribute \src "ls180.v:8900.48-8900.127" - wire $or$ls180.v:8900$2868_Y + wire $or$ls180.v:8900$2870_Y attribute \src "ls180.v:8901.47-8901.124" - wire $or$ls180.v:8901$2869_Y + wire $or$ls180.v:8901$2871_Y attribute \src "ls180.v:3358.46-3358.94" wire width 13 $sshl$ls180.v:3358$231_Y attribute \src "ls180.v:3515.46-3515.94" @@ -248302,55 +248306,55 @@ module \ls180 attribute \src "ls180.v:5836.40-5836.76" wire width 5 $sub$ls180.v:5836$1169_Y attribute \src "ls180.v:7776.31-7776.60" - wire width 32 $sub$ls180.v:7776$2607_Y + wire width 32 $sub$ls180.v:7776$2609_Y attribute \src "ls180.v:7813.31-7813.61" - wire width 10 $sub$ls180.v:7813$2624_Y + wire width 10 $sub$ls180.v:7813$2626_Y attribute \src "ls180.v:7819.34-7819.67" - wire $sub$ls180.v:7819$2625_Y + wire $sub$ls180.v:7819$2627_Y attribute \src "ls180.v:7830.36-7830.69" - wire $sub$ls180.v:7830$2628_Y + wire $sub$ls180.v:7830$2630_Y attribute \src "ls180.v:7894.59-7894.116" - wire width 4 $sub$ls180.v:7894$2646_Y + wire width 4 $sub$ls180.v:7894$2648_Y attribute \src "ls180.v:7913.46-7913.90" - wire width 3 $sub$ls180.v:7913$2650_Y + wire width 3 $sub$ls180.v:7913$2652_Y attribute \src "ls180.v:7940.59-7940.116" - wire width 4 $sub$ls180.v:7940$2662_Y + wire width 4 $sub$ls180.v:7940$2664_Y attribute \src "ls180.v:7959.46-7959.90" - wire width 3 $sub$ls180.v:7959$2666_Y + wire width 3 $sub$ls180.v:7959$2668_Y attribute \src "ls180.v:7986.59-7986.116" - wire width 4 $sub$ls180.v:7986$2678_Y + wire width 4 $sub$ls180.v:7986$2680_Y attribute \src "ls180.v:8005.46-8005.90" - wire width 3 $sub$ls180.v:8005$2682_Y + wire width 3 $sub$ls180.v:8005$2684_Y attribute \src "ls180.v:8032.59-8032.116" - wire width 4 $sub$ls180.v:8032$2694_Y + wire width 4 $sub$ls180.v:8032$2696_Y attribute \src "ls180.v:8051.46-8051.90" - wire width 3 $sub$ls180.v:8051$2698_Y + wire width 3 $sub$ls180.v:8051$2700_Y attribute \src "ls180.v:8062.25-8062.48" - wire width 5 $sub$ls180.v:8062$2702_Y + wire width 5 $sub$ls180.v:8062$2704_Y attribute \src "ls180.v:8069.25-8069.48" - wire width 4 $sub$ls180.v:8069$2705_Y + wire width 4 $sub$ls180.v:8069$2707_Y attribute \src "ls180.v:8201.33-8201.64" - wire $sub$ls180.v:8201$2710_Y + wire $sub$ls180.v:8201$2712_Y attribute \src "ls180.v:8216.33-8216.64" - wire width 3 $sub$ls180.v:8216$2713_Y + wire width 3 $sub$ls180.v:8216$2715_Y attribute \src "ls180.v:8343.33-8343.64" - wire width 5 $sub$ls180.v:8343$2772_Y + wire width 5 $sub$ls180.v:8343$2774_Y attribute \src "ls180.v:8365.33-8365.64" - wire width 5 $sub$ls180.v:8365$2783_Y + wire width 5 $sub$ls180.v:8365$2785_Y attribute \src "ls180.v:8400.34-8400.66" - wire width 3 $sub$ls180.v:8400$2788_Y + wire width 3 $sub$ls180.v:8400$2790_Y attribute \src "ls180.v:8435.32-8435.62" - wire width 3 $sub$ls180.v:8435$2793_Y + wire width 3 $sub$ls180.v:8435$2795_Y attribute \src "ls180.v:8459.30-8459.53" - wire width 32 $sub$ls180.v:8459$2796_Y + wire width 32 $sub$ls180.v:8459$2798_Y attribute \src "ls180.v:8473.30-8473.53" - wire width 32 $sub$ls180.v:8473$2800_Y + wire width 32 $sub$ls180.v:8473$2802_Y attribute \src "ls180.v:8876.36-8876.70" - wire width 6 $sub$ls180.v:8876$2861_Y + wire width 6 $sub$ls180.v:8876$2863_Y attribute \src "ls180.v:8974.36-8974.70" - wire width 6 $sub$ls180.v:8974$2883_Y + wire width 6 $sub$ls180.v:8974$2885_Y attribute \src "ls180.v:9087.22-9087.42" - wire width 20 $sub$ls180.v:9087$2890_Y + wire width 20 $sub$ls180.v:9087$2892_Y attribute \src "ls180.v:5113.353-5113.425" wire $xor$ls180.v:5113$860_Y attribute \src "ls180.v:5113.200-5113.272" @@ -250563,24 +250567,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:13.19-13.23" - wire width 3 input 9 \eint - attribute \src "ls180.v:179.12-179.18" + attribute \src "ls180.v:16.19-16.23" + wire width 3 input 12 \eint + attribute \src "ls180.v:182.12-182.18" wire width 3 \eint_1 - attribute \src "ls180.v:40.21-40.27" - wire width 16 output 36 \gpio_i - attribute \src "ls180.v:41.20-41.26" - wire width 16 output 37 \gpio_o - attribute \src "ls180.v:42.20-42.27" - wire width 16 output 38 \gpio_oe - attribute \src "ls180.v:9.14-9.21" - wire output 5 \i2c_scl + attribute \src "ls180.v:5.21-5.27" + wire width 16 output 1 \gpio_i + attribute \src "ls180.v:6.20-6.26" + wire width 16 output 2 \gpio_o + attribute \src "ls180.v:7.20-7.27" + wire width 16 output 3 \gpio_oe + attribute \src "ls180.v:8.14-8.21" + wire output 4 \i2c_scl + attribute \src "ls180.v:9.14-9.23" + wire output 5 \i2c_sda_i attribute \src "ls180.v:10.14-10.23" - wire output 6 \i2c_sda_i - attribute \src "ls180.v:11.14-11.23" - wire output 7 \i2c_sda_o - attribute \src "ls180.v:12.14-12.24" - wire output 8 \i2c_sda_oe + wire output 6 \i2c_sda_o + attribute \src "ls180.v:11.14-11.24" + wire output 7 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -250939,71 +250943,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:204.12-204.66" + attribute \src "ls180.v:171.12-171.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:205.13-205.67" + attribute \src "ls180.v:172.13-172.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:206.13-206.68" + attribute \src "ls180.v:173.13-173.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:175.6-175.61" + attribute \src "ls180.v:174.6-174.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:176.5-176.62" + attribute \src "ls180.v:175.5-175.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:177.6-177.63" + attribute \src "ls180.v:176.6-176.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:178.6-178.64" + attribute \src "ls180.v:177.6-177.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:180.6-180.64" + attribute \src "ls180.v:200.6-200.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:181.5-181.65" + attribute \src "ls180.v:201.5-201.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:182.6-182.66" + attribute \src "ls180.v:202.6-202.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:183.6-183.67" + attribute \src "ls180.v:203.6-203.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:184.11-184.72" + attribute \src "ls180.v:204.11-204.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:185.12-185.73" + attribute \src "ls180.v:205.12-205.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:186.6-186.68" + attribute \src "ls180.v:206.6-206.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:187.13-187.68" + attribute \src "ls180.v:188.13-188.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:196.12-196.68" + attribute \src "ls180.v:197.12-197.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:193.6-193.65" + attribute \src "ls180.v:194.6-194.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:195.6-195.63" + attribute \src "ls180.v:196.6-196.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:194.6-194.64" + attribute \src "ls180.v:195.6-195.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:197.12-197.68" + attribute \src "ls180.v:198.12-198.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:188.12-188.70" + attribute \src "ls180.v:189.12-189.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:189.13-189.71" + attribute \src "ls180.v:190.13-190.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:190.6-190.65" + attribute \src "ls180.v:191.6-191.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:192.6-192.65" + attribute \src "ls180.v:193.6-193.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:191.6-191.64" + attribute \src "ls180.v:192.6-192.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:171.6-171.67" + attribute \src "ls180.v:184.6-184.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:173.6-173.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:174.6-174.68" + attribute \src "ls180.v:187.6-187.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:172.6-172.68" + attribute \src "ls180.v:185.6-185.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:199.6-199.67" + attribute \src "ls180.v:178.6-178.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:201.6-201.68" + attribute \src "ls180.v:180.6-180.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:202.6-202.68" + attribute \src "ls180.v:181.6-181.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:200.6-200.68" + attribute \src "ls180.v:179.6-179.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -254333,50 +254337,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:39.19-39.22" - wire width 2 output 35 \pwm - attribute \src "ls180.v:203.12-203.17" + attribute \src "ls180.v:17.19-17.22" + wire width 2 output 13 \pwm + attribute \src "ls180.v:183.12-183.17" wire width 2 \pwm_1 - attribute \src "ls180.v:14.13-14.23" - wire output 10 \sdcard_clk - attribute \src "ls180.v:15.14-15.26" - wire output 11 \sdcard_cmd_i - attribute \src "ls180.v:16.13-16.25" - wire output 12 \sdcard_cmd_o - attribute \src "ls180.v:17.13-17.26" - wire output 13 \sdcard_cmd_oe - attribute \src "ls180.v:18.20-18.33" - wire width 4 output 14 \sdcard_data_i - attribute \src "ls180.v:19.19-19.32" - wire width 4 output 15 \sdcard_data_o - attribute \src "ls180.v:20.13-20.27" - wire output 16 \sdcard_data_oe - attribute \src "ls180.v:21.20-21.27" - wire width 13 output 17 \sdram_a - attribute \src "ls180.v:30.19-30.27" - wire width 2 output 26 \sdram_ba - attribute \src "ls180.v:27.13-27.24" - wire output 23 \sdram_cas_n - attribute \src "ls180.v:29.13-29.22" - wire output 25 \sdram_cke - attribute \src "ls180.v:32.13-32.24" - wire output 28 \sdram_clock - attribute \src "ls180.v:198.6-198.19" - wire \sdram_clock_1 - attribute \src "ls180.v:28.13-28.23" - wire output 24 \sdram_cs_n + attribute \src "ls180.v:36.13-36.23" + wire output 32 \sdcard_clk + attribute \src "ls180.v:37.14-37.26" + wire output 33 \sdcard_cmd_i + attribute \src "ls180.v:38.13-38.25" + wire output 34 \sdcard_cmd_o + attribute \src "ls180.v:39.13-39.26" + wire output 35 \sdcard_cmd_oe + attribute \src "ls180.v:40.20-40.33" + wire width 4 output 36 \sdcard_data_i + attribute \src "ls180.v:41.19-41.32" + wire width 4 output 37 \sdcard_data_o + attribute \src "ls180.v:42.13-42.27" + wire output 38 \sdcard_data_oe + attribute \src "ls180.v:22.20-22.27" + wire width 13 output 18 \sdram_a attribute \src "ls180.v:31.19-31.27" - wire width 2 output 27 \sdram_dm - attribute \src "ls180.v:22.21-22.31" - wire width 16 output 18 \sdram_dq_i - attribute \src "ls180.v:23.20-23.30" - wire width 16 output 19 \sdram_dq_o - attribute \src "ls180.v:24.13-24.24" - wire output 20 \sdram_dq_oe - attribute \src "ls180.v:26.13-26.24" - wire output 22 \sdram_ras_n - attribute \src "ls180.v:25.13-25.23" - wire output 21 \sdram_we_n + wire width 2 output 27 \sdram_ba + attribute \src "ls180.v:28.13-28.24" + wire output 24 \sdram_cas_n + attribute \src "ls180.v:30.13-30.22" + wire output 26 \sdram_cke + attribute \src "ls180.v:33.13-33.24" + wire output 29 \sdram_clock + attribute \src "ls180.v:199.6-199.19" + wire \sdram_clock_1 + attribute \src "ls180.v:29.13-29.23" + wire output 25 \sdram_cs_n + attribute \src "ls180.v:32.19-32.27" + wire width 2 output 28 \sdram_dm + attribute \src "ls180.v:23.21-23.31" + wire width 16 output 19 \sdram_dq_i + attribute \src "ls180.v:24.20-24.30" + wire width 16 output 20 \sdram_dq_o + attribute \src "ls180.v:25.13-25.24" + wire output 21 \sdram_dq_oe + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_ras_n + attribute \src "ls180.v:26.13-26.23" + wire output 22 \sdram_we_n attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk attribute \src "ls180.v:2764.6-2764.17" @@ -254515,22 +254519,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:5.13-5.26" - wire output 1 \spimaster_clk - attribute \src "ls180.v:7.13-7.27" - wire output 3 \spimaster_cs_n - attribute \src "ls180.v:8.13-8.27" - wire input 4 \spimaster_miso - attribute \src "ls180.v:6.13-6.27" - wire output 2 \spimaster_mosi - attribute \src "ls180.v:33.13-33.26" - wire output 29 \spisdcard_clk - attribute \src "ls180.v:35.13-35.27" - wire output 31 \spisdcard_cs_n - attribute \src "ls180.v:36.13-36.27" - wire input 32 \spisdcard_miso - attribute \src "ls180.v:34.13-34.27" - wire output 30 \spisdcard_mosi + attribute \src "ls180.v:18.13-18.26" + wire output 14 \spimaster_clk + attribute \src "ls180.v:20.13-20.27" + wire output 16 \spimaster_cs_n + attribute \src "ls180.v:21.13-21.27" + wire input 17 \spimaster_miso + attribute \src "ls180.v:19.13-19.27" + wire output 15 \spimaster_mosi + attribute \src "ls180.v:12.13-12.26" + wire output 8 \spisdcard_clk + attribute \src "ls180.v:14.13-14.27" + wire output 10 \spisdcard_cs_n + attribute \src "ls180.v:15.13-15.27" + wire input 11 \spisdcard_miso + attribute \src "ls180.v:13.13-13.27" + wire output 9 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:339.6-339.15" @@ -254545,10 +254549,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:38.13-38.20" - wire input 34 \uart_rx - attribute \src "ls180.v:37.13-37.20" - wire output 33 \uart_tx + attribute \src "ls180.v:35.13-35.20" + wire input 31 \uart_rx + attribute \src "ls180.v:34.13-34.20" + wire output 30 \uart_tx attribute \src "ls180.v:10351.12-10351.15" memory width 64 size 64 \mem attribute \src "ls180.v:10379.12-10379.17" @@ -254851,7 +254855,7 @@ module \ls180 connect \Y $add$ls180.v:5758$1161_Y end attribute \src "ls180.v:7765.36-7765.70" - cell $add $add$ls180.v:7765$2602 + cell $add $add$ls180.v:7765$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254859,10 +254863,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7765$2602_Y + connect \Y $add$ls180.v:7765$2604_Y end attribute \src "ls180.v:7866.37-7866.72" - cell $add $add$ls180.v:7866$2635 + cell $add $add$ls180.v:7866$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254870,10 +254874,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7866$2635_Y + connect \Y $add$ls180.v:7866$2637_Y end attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2639 + cell $add $add$ls180.v:7883$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254881,10 +254885,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7883$2639_Y + connect \Y $add$ls180.v:7883$2641_Y end attribute \src "ls180.v:7886.60-7886.119" - cell $add $add$ls180.v:7886$2640 + cell $add $add$ls180.v:7886$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254892,10 +254896,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7886$2640_Y + connect \Y $add$ls180.v:7886$2642_Y end attribute \src "ls180.v:7890.59-7890.116" - cell $add $add$ls180.v:7890$2645 + cell $add $add$ls180.v:7890$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254903,10 +254907,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7890$2645_Y + connect \Y $add$ls180.v:7890$2647_Y end attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2655 + cell $add $add$ls180.v:7929$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254914,10 +254918,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7929$2655_Y + connect \Y $add$ls180.v:7929$2657_Y end attribute \src "ls180.v:7932.60-7932.119" - cell $add $add$ls180.v:7932$2656 + cell $add $add$ls180.v:7932$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254925,10 +254929,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7932$2656_Y + connect \Y $add$ls180.v:7932$2658_Y end attribute \src "ls180.v:7936.59-7936.116" - cell $add $add$ls180.v:7936$2661 + cell $add $add$ls180.v:7936$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254936,10 +254940,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7936$2661_Y + connect \Y $add$ls180.v:7936$2663_Y end attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2671 + cell $add $add$ls180.v:7975$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254947,10 +254951,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7975$2671_Y + connect \Y $add$ls180.v:7975$2673_Y end attribute \src "ls180.v:7978.60-7978.119" - cell $add $add$ls180.v:7978$2672 + cell $add $add$ls180.v:7978$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254958,10 +254962,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7978$2672_Y + connect \Y $add$ls180.v:7978$2674_Y end attribute \src "ls180.v:7982.59-7982.116" - cell $add $add$ls180.v:7982$2677 + cell $add $add$ls180.v:7982$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254969,10 +254973,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7982$2677_Y + connect \Y $add$ls180.v:7982$2679_Y end attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2687 + cell $add $add$ls180.v:8021$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254980,10 +254984,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:8021$2687_Y + connect \Y $add$ls180.v:8021$2689_Y end attribute \src "ls180.v:8024.60-8024.119" - cell $add $add$ls180.v:8024$2688 + cell $add $add$ls180.v:8024$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254991,10 +254995,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:8024$2688_Y + connect \Y $add$ls180.v:8024$2690_Y end attribute \src "ls180.v:8028.59-8028.116" - cell $add $add$ls180.v:8028$2693 + cell $add $add$ls180.v:8028$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255002,10 +255006,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:8028$2693_Y + connect \Y $add$ls180.v:8028$2695_Y end attribute \src "ls180.v:8258.34-8258.66" - cell $add $add$ls180.v:8258$2747 + cell $add $add$ls180.v:8258$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255013,10 +255017,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8258$2747_Y + connect \Y $add$ls180.v:8258$2749_Y end attribute \src "ls180.v:8274.73-8274.131" - cell $add $add$ls180.v:8274$2750 + cell $add $add$ls180.v:8274$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255024,10 +255028,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8274$2750_Y + connect \Y $add$ls180.v:8274$2752_Y end attribute \src "ls180.v:8287.34-8287.66" - cell $add $add$ls180.v:8287$2754 + cell $add $add$ls180.v:8287$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255035,10 +255039,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8287$2754_Y + connect \Y $add$ls180.v:8287$2756_Y end attribute \src "ls180.v:8306.73-8306.131" - cell $add $add$ls180.v:8306$2757 + cell $add $add$ls180.v:8306$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255046,10 +255050,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8306$2757_Y + connect \Y $add$ls180.v:8306$2759_Y end attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2765 + cell $add $add$ls180.v:8332$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255057,10 +255061,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8332$2765_Y + connect \Y $add$ls180.v:8332$2767_Y end attribute \src "ls180.v:8335.33-8335.65" - cell $add $add$ls180.v:8335$2766 + cell $add $add$ls180.v:8335$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255068,10 +255072,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8335$2766_Y + connect \Y $add$ls180.v:8335$2768_Y end attribute \src "ls180.v:8339.33-8339.64" - cell $add $add$ls180.v:8339$2771 + cell $add $add$ls180.v:8339$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255079,10 +255083,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8339$2771_Y + connect \Y $add$ls180.v:8339$2773_Y end attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2776 + cell $add $add$ls180.v:8354$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255090,10 +255094,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8354$2776_Y + connect \Y $add$ls180.v:8354$2778_Y end attribute \src "ls180.v:8357.33-8357.65" - cell $add $add$ls180.v:8357$2777 + cell $add $add$ls180.v:8357$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255101,10 +255105,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8357$2777_Y + connect \Y $add$ls180.v:8357$2779_Y end attribute \src "ls180.v:8361.33-8361.64" - cell $add $add$ls180.v:8361$2782 + cell $add $add$ls180.v:8361$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255112,10 +255116,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8361$2782_Y + connect \Y $add$ls180.v:8361$2784_Y end attribute \src "ls180.v:8382.35-8382.70" - cell $add $add$ls180.v:8382$2784 + cell $add $add$ls180.v:8382$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255123,10 +255127,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8382$2784_Y + connect \Y $add$ls180.v:8382$2786_Y end attribute \src "ls180.v:8417.34-8417.68" - cell $add $add$ls180.v:8417$2789 + cell $add $add$ls180.v:8417$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255134,10 +255138,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8417$2789_Y + connect \Y $add$ls180.v:8417$2791_Y end attribute \src "ls180.v:8453.25-8453.49" - cell $add $add$ls180.v:8453$2794 + cell $add $add$ls180.v:8453$2796 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255145,10 +255149,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8453$2794_Y + connect \Y $add$ls180.v:8453$2796_Y end attribute \src "ls180.v:8467.25-8467.49" - cell $add $add$ls180.v:8467$2798 + cell $add $add$ls180.v:8467$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255156,10 +255160,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8467$2798_Y + connect \Y $add$ls180.v:8467$2800_Y end attribute \src "ls180.v:8481.31-8481.61" - cell $add $add$ls180.v:8481$2803 + cell $add $add$ls180.v:8481$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -255167,10 +255171,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8481$2803_Y + connect \Y $add$ls180.v:8481$2805_Y end attribute \src "ls180.v:8504.45-8504.88" - cell $add $add$ls180.v:8504$2807 + cell $add $add$ls180.v:8504$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255178,10 +255182,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8504$2807_Y + connect \Y $add$ls180.v:8504$2809_Y end attribute \src "ls180.v:8550.71-8550.114" - cell $add $add$ls180.v:8550$2813 + cell $add $add$ls180.v:8550$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255189,10 +255193,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8550$2813_Y + connect \Y $add$ls180.v:8550$2815_Y end attribute \src "ls180.v:8585.46-8585.90" - cell $add $add$ls180.v:8585$2819 + cell $add $add$ls180.v:8585$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255200,10 +255204,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8585$2819_Y + connect \Y $add$ls180.v:8585$2821_Y end attribute \src "ls180.v:8631.72-8631.116" - cell $add $add$ls180.v:8631$2825 + cell $add $add$ls180.v:8631$2827 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255211,10 +255215,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8631$2825_Y + connect \Y $add$ls180.v:8631$2827_Y end attribute \src "ls180.v:8664.47-8664.92" - cell $add $add$ls180.v:8664$2831 + cell $add $add$ls180.v:8664$2833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255222,10 +255226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8664$2831_Y + connect \Y $add$ls180.v:8664$2833_Y end attribute \src "ls180.v:8692.73-8692.118" - cell $add $add$ls180.v:8692$2837 + cell $add $add$ls180.v:8692$2839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255233,10 +255237,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8692$2837_Y + connect \Y $add$ls180.v:8692$2839_Y end attribute \src "ls180.v:8804.39-8804.75" - cell $add $add$ls180.v:8804$2850 + cell $add $add$ls180.v:8804$2852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255244,10 +255248,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8804$2850_Y + connect \Y $add$ls180.v:8804$2852_Y end attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2854 + cell $add $add$ls180.v:8865$2856 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255255,10 +255259,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8865$2854_Y + connect \Y $add$ls180.v:8865$2856_Y end attribute \src "ls180.v:8868.37-8868.73" - cell $add $add$ls180.v:8868$2855 + cell $add $add$ls180.v:8868$2857 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255266,10 +255270,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8868$2855_Y + connect \Y $add$ls180.v:8868$2857_Y end attribute \src "ls180.v:8872.36-8872.70" - cell $add $add$ls180.v:8872$2860 + cell $add $add$ls180.v:8872$2862 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255277,10 +255281,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8872$2860_Y + connect \Y $add$ls180.v:8872$2862_Y end attribute \src "ls180.v:8887.41-8887.80" - cell $add $add$ls180.v:8887$2864 + cell $add $add$ls180.v:8887$2866 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255288,10 +255292,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8887$2864_Y + connect \Y $add$ls180.v:8887$2866_Y end attribute \src "ls180.v:8933.67-8933.106" - cell $add $add$ls180.v:8933$2870 + cell $add $add$ls180.v:8933$2872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255299,10 +255303,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8933$2870_Y + connect \Y $add$ls180.v:8933$2872_Y end attribute \src "ls180.v:8959.39-8959.76" - cell $add $add$ls180.v:8959$2872 + cell $add $add$ls180.v:8959$2874 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255310,10 +255314,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8959$2872_Y + connect \Y $add$ls180.v:8959$2874_Y end attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2876 + cell $add $add$ls180.v:8963$2878 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255321,10 +255325,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8963$2876_Y + connect \Y $add$ls180.v:8963$2878_Y end attribute \src "ls180.v:8966.37-8966.73" - cell $add $add$ls180.v:8966$2877 + cell $add $add$ls180.v:8966$2879 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255332,10 +255336,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8966$2877_Y + connect \Y $add$ls180.v:8966$2879_Y end attribute \src "ls180.v:8970.36-8970.70" - cell $add $add$ls180.v:8970$2882 + cell $add $add$ls180.v:8970$2884 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255343,7 +255347,7 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8970$2882_Y + connect \Y $add$ls180.v:8970$2884_Y end attribute \src "ls180.v:2929.9-2929.90" cell $and $and$ls180.v:2929$53 @@ -267775,19 +267779,41 @@ module \ls180 connect \B \main_sdram_cmd_payload_is_write connect \Y $and$ls180.v:7468$2564_Y end + attribute \src "ls180.v:7687.18-7687.68" + cell $and $and$ls180.v:7687$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [0] + connect \Y $and$ls180.v:7687$2571_Y + end + attribute \src "ls180.v:7688.18-7688.68" + cell $and $and$ls180.v:7688$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [1] + connect \Y $and$ls180.v:7688$2572_Y + end attribute \src "ls180.v:7690.17-7690.67" - cell $and $and$ls180.v:7690$2572 + cell $and $and$ls180.v:7690$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7690$2571_Y + connect \A $not$ls180.v:7690$2573_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7690$2572_Y + connect \Y $and$ls180.v:7690$2574_Y end attribute \src "ls180.v:7769.8-7769.67" - cell $and $and$ls180.v:7769$2603 + cell $and $and$ls180.v:7769$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267795,32 +267821,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7769$2603_Y + connect \Y $and$ls180.v:7769$2605_Y end attribute \src "ls180.v:7769.7-7769.102" - cell $and $and$ls180.v:7769$2605 + cell $and $and$ls180.v:7769$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7769$2603_Y - connect \B $not$ls180.v:7769$2604_Y - connect \Y $and$ls180.v:7769$2605_Y + connect \A $and$ls180.v:7769$2605_Y + connect \B $not$ls180.v:7769$2606_Y + connect \Y $and$ls180.v:7769$2607_Y end attribute \src "ls180.v:7788.7-7788.75" - cell $and $and$ls180.v:7788$2609 + cell $and $and$ls180.v:7788$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7788$2608_Y + connect \A $not$ls180.v:7788$2610_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7788$2609_Y + connect \Y $and$ls180.v:7788$2611_Y end attribute \src "ls180.v:7792.8-7792.65" - cell $and $and$ls180.v:7792$2610 + cell $and $and$ls180.v:7792$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267828,21 +267854,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7792$2610_Y + connect \Y $and$ls180.v:7792$2612_Y end attribute \src "ls180.v:7792.7-7792.99" - cell $and $and$ls180.v:7792$2612 + cell $and $and$ls180.v:7792$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7792$2610_Y - connect \B $not$ls180.v:7792$2611_Y - connect \Y $and$ls180.v:7792$2612_Y + connect \A $and$ls180.v:7792$2612_Y + connect \B $not$ls180.v:7792$2613_Y + connect \Y $and$ls180.v:7792$2614_Y end attribute \src "ls180.v:7796.8-7796.65" - cell $and $and$ls180.v:7796$2613 + cell $and $and$ls180.v:7796$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267850,21 +267876,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7796$2613_Y + connect \Y $and$ls180.v:7796$2615_Y end attribute \src "ls180.v:7796.7-7796.99" - cell $and $and$ls180.v:7796$2615 + cell $and $and$ls180.v:7796$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7796$2613_Y - connect \B $not$ls180.v:7796$2614_Y - connect \Y $and$ls180.v:7796$2615_Y + connect \A $and$ls180.v:7796$2615_Y + connect \B $not$ls180.v:7796$2616_Y + connect \Y $and$ls180.v:7796$2617_Y end attribute \src "ls180.v:7800.8-7800.65" - cell $and $and$ls180.v:7800$2616 + cell $and $and$ls180.v:7800$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267872,21 +267898,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7800$2616_Y + connect \Y $and$ls180.v:7800$2618_Y end attribute \src "ls180.v:7800.7-7800.99" - cell $and $and$ls180.v:7800$2618 + cell $and $and$ls180.v:7800$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2616_Y - connect \B $not$ls180.v:7800$2617_Y - connect \Y $and$ls180.v:7800$2618_Y + connect \A $and$ls180.v:7800$2618_Y + connect \B $not$ls180.v:7800$2619_Y + connect \Y $and$ls180.v:7800$2620_Y end attribute \src "ls180.v:7804.8-7804.65" - cell $and $and$ls180.v:7804$2619 + cell $and $and$ls180.v:7804$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267894,43 +267920,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7804$2619_Y + connect \Y $and$ls180.v:7804$2621_Y end attribute \src "ls180.v:7804.7-7804.99" - cell $and $and$ls180.v:7804$2621 + cell $and $and$ls180.v:7804$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7804$2619_Y - connect \B $not$ls180.v:7804$2620_Y - connect \Y $and$ls180.v:7804$2621_Y + connect \A $and$ls180.v:7804$2621_Y + connect \B $not$ls180.v:7804$2622_Y + connect \Y $and$ls180.v:7804$2623_Y end attribute \src "ls180.v:7812.7-7812.56" - cell $and $and$ls180.v:7812$2623 + cell $and $and$ls180.v:7812$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7812$2622_Y - connect \Y $and$ls180.v:7812$2623_Y + connect \B $not$ls180.v:7812$2624_Y + connect \Y $and$ls180.v:7812$2625_Y end attribute \src "ls180.v:7840.7-7840.75" - cell $and $and$ls180.v:7840$2630 + cell $and $and$ls180.v:7840$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7840$2629_Y - connect \Y $and$ls180.v:7840$2630_Y + connect \B $eq$ls180.v:7840$2631_Y + connect \Y $and$ls180.v:7840$2632_Y end attribute \src "ls180.v:7882.8-7882.131" - cell $and $and$ls180.v:7882$2636 + cell $and $and$ls180.v:7882$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267938,21 +267964,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7882$2636_Y + connect \Y $and$ls180.v:7882$2638_Y end attribute \src "ls180.v:7882.7-7882.190" - cell $and $and$ls180.v:7882$2638 + cell $and $and$ls180.v:7882$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7882$2636_Y - connect \B $not$ls180.v:7882$2637_Y - connect \Y $and$ls180.v:7882$2638_Y + connect \A $and$ls180.v:7882$2638_Y + connect \B $not$ls180.v:7882$2639_Y + connect \Y $and$ls180.v:7882$2640_Y end attribute \src "ls180.v:7888.8-7888.131" - cell $and $and$ls180.v:7888$2641 + cell $and $and$ls180.v:7888$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267960,21 +267986,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7888$2641_Y + connect \Y $and$ls180.v:7888$2643_Y end attribute \src "ls180.v:7888.7-7888.190" - cell $and $and$ls180.v:7888$2643 + cell $and $and$ls180.v:7888$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7888$2641_Y - connect \B $not$ls180.v:7888$2642_Y - connect \Y $and$ls180.v:7888$2643_Y + connect \A $and$ls180.v:7888$2643_Y + connect \B $not$ls180.v:7888$2644_Y + connect \Y $and$ls180.v:7888$2645_Y end attribute \src "ls180.v:7928.8-7928.131" - cell $and $and$ls180.v:7928$2652 + cell $and $and$ls180.v:7928$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267982,21 +268008,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7928$2652_Y + connect \Y $and$ls180.v:7928$2654_Y end attribute \src "ls180.v:7928.7-7928.190" - cell $and $and$ls180.v:7928$2654 + cell $and $and$ls180.v:7928$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7928$2652_Y - connect \B $not$ls180.v:7928$2653_Y - connect \Y $and$ls180.v:7928$2654_Y + connect \A $and$ls180.v:7928$2654_Y + connect \B $not$ls180.v:7928$2655_Y + connect \Y $and$ls180.v:7928$2656_Y end attribute \src "ls180.v:7934.8-7934.131" - cell $and $and$ls180.v:7934$2657 + cell $and $and$ls180.v:7934$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268004,21 +268030,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7934$2657_Y + connect \Y $and$ls180.v:7934$2659_Y end attribute \src "ls180.v:7934.7-7934.190" - cell $and $and$ls180.v:7934$2659 + cell $and $and$ls180.v:7934$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7934$2657_Y - connect \B $not$ls180.v:7934$2658_Y - connect \Y $and$ls180.v:7934$2659_Y + connect \A $and$ls180.v:7934$2659_Y + connect \B $not$ls180.v:7934$2660_Y + connect \Y $and$ls180.v:7934$2661_Y end attribute \src "ls180.v:7974.8-7974.131" - cell $and $and$ls180.v:7974$2668 + cell $and $and$ls180.v:7974$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268026,21 +268052,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7974$2668_Y + connect \Y $and$ls180.v:7974$2670_Y end attribute \src "ls180.v:7974.7-7974.190" - cell $and $and$ls180.v:7974$2670 + cell $and $and$ls180.v:7974$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7974$2668_Y - connect \B $not$ls180.v:7974$2669_Y - connect \Y $and$ls180.v:7974$2670_Y + connect \A $and$ls180.v:7974$2670_Y + connect \B $not$ls180.v:7974$2671_Y + connect \Y $and$ls180.v:7974$2672_Y end attribute \src "ls180.v:7980.8-7980.131" - cell $and $and$ls180.v:7980$2673 + cell $and $and$ls180.v:7980$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268048,21 +268074,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7980$2673_Y + connect \Y $and$ls180.v:7980$2675_Y end attribute \src "ls180.v:7980.7-7980.190" - cell $and $and$ls180.v:7980$2675 + cell $and $and$ls180.v:7980$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7980$2673_Y - connect \B $not$ls180.v:7980$2674_Y - connect \Y $and$ls180.v:7980$2675_Y + connect \A $and$ls180.v:7980$2675_Y + connect \B $not$ls180.v:7980$2676_Y + connect \Y $and$ls180.v:7980$2677_Y end attribute \src "ls180.v:8020.8-8020.131" - cell $and $and$ls180.v:8020$2684 + cell $and $and$ls180.v:8020$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268070,21 +268096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8020$2684_Y + connect \Y $and$ls180.v:8020$2686_Y end attribute \src "ls180.v:8020.7-8020.190" - cell $and $and$ls180.v:8020$2686 + cell $and $and$ls180.v:8020$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8020$2684_Y - connect \B $not$ls180.v:8020$2685_Y - connect \Y $and$ls180.v:8020$2686_Y + connect \A $and$ls180.v:8020$2686_Y + connect \B $not$ls180.v:8020$2687_Y + connect \Y $and$ls180.v:8020$2688_Y end attribute \src "ls180.v:8026.8-8026.131" - cell $and $and$ls180.v:8026$2689 + cell $and $and$ls180.v:8026$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268092,109 +268118,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8026$2689_Y + connect \Y $and$ls180.v:8026$2691_Y end attribute \src "ls180.v:8026.7-8026.190" - cell $and $and$ls180.v:8026$2691 + cell $and $and$ls180.v:8026$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8026$2689_Y - connect \B $not$ls180.v:8026$2690_Y - connect \Y $and$ls180.v:8026$2691_Y + connect \A $and$ls180.v:8026$2691_Y + connect \B $not$ls180.v:8026$2692_Y + connect \Y $and$ls180.v:8026$2693_Y end attribute \src "ls180.v:8223.48-8223.124" - cell $and $and$ls180.v:8223$2716 + cell $and $and$ls180.v:8223$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2715_Y + connect \A $eq$ls180.v:8223$2717_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8223$2716_Y + connect \Y $and$ls180.v:8223$2718_Y end attribute \src "ls180.v:8223.130-8223.206" - cell $and $and$ls180.v:8223$2719 + cell $and $and$ls180.v:8223$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2718_Y + connect \A $eq$ls180.v:8223$2720_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8223$2719_Y + connect \Y $and$ls180.v:8223$2721_Y end attribute \src "ls180.v:8223.212-8223.288" - cell $and $and$ls180.v:8223$2722 + cell $and $and$ls180.v:8223$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2721_Y + connect \A $eq$ls180.v:8223$2723_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8223$2722_Y + connect \Y $and$ls180.v:8223$2724_Y end attribute \src "ls180.v:8223.294-8223.370" - cell $and $and$ls180.v:8223$2725 + cell $and $and$ls180.v:8223$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2724_Y + connect \A $eq$ls180.v:8223$2726_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8223$2725_Y + connect \Y $and$ls180.v:8223$2727_Y end attribute \src "ls180.v:8224.49-8224.125" - cell $and $and$ls180.v:8224$2728 + cell $and $and$ls180.v:8224$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2727_Y + connect \A $eq$ls180.v:8224$2729_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8224$2728_Y + connect \Y $and$ls180.v:8224$2730_Y end attribute \src "ls180.v:8224.131-8224.207" - cell $and $and$ls180.v:8224$2731 + cell $and $and$ls180.v:8224$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2730_Y + connect \A $eq$ls180.v:8224$2732_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8224$2731_Y + connect \Y $and$ls180.v:8224$2733_Y end attribute \src "ls180.v:8224.213-8224.289" - cell $and $and$ls180.v:8224$2734 + cell $and $and$ls180.v:8224$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2733_Y + connect \A $eq$ls180.v:8224$2735_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8224$2734_Y + connect \Y $and$ls180.v:8224$2736_Y end attribute \src "ls180.v:8224.295-8224.371" - cell $and $and$ls180.v:8224$2737 + cell $and $and$ls180.v:8224$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2736_Y + connect \A $eq$ls180.v:8224$2738_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8224$2737_Y + connect \Y $and$ls180.v:8224$2739_Y end attribute \src "ls180.v:8243.8-8243.49" - cell $and $and$ls180.v:8243$2740 + cell $and $and$ls180.v:8243$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268202,10 +268228,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8243$2740_Y + connect \Y $and$ls180.v:8243$2742_Y end attribute \src "ls180.v:8246.8-8246.53" - cell $and $and$ls180.v:8246$2741 + cell $and $and$ls180.v:8246$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268213,32 +268239,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8246$2741_Y + connect \Y $and$ls180.v:8246$2743_Y end attribute \src "ls180.v:8251.8-8251.59" - cell $and $and$ls180.v:8251$2743 + cell $and $and$ls180.v:8251$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8251$2742_Y - connect \Y $and$ls180.v:8251$2743_Y + connect \B $not$ls180.v:8251$2744_Y + connect \Y $and$ls180.v:8251$2745_Y end attribute \src "ls180.v:8251.7-8251.90" - cell $and $and$ls180.v:8251$2745 + cell $and $and$ls180.v:8251$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8251$2743_Y - connect \B $not$ls180.v:8251$2744_Y - connect \Y $and$ls180.v:8251$2745_Y + connect \A $and$ls180.v:8251$2745_Y + connect \B $not$ls180.v:8251$2746_Y + connect \Y $and$ls180.v:8251$2747_Y end attribute \src "ls180.v:8257.8-8257.59" - cell $and $and$ls180.v:8257$2746 + cell $and $and$ls180.v:8257$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268246,43 +268272,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8257$2746_Y + connect \Y $and$ls180.v:8257$2748_Y end attribute \src "ls180.v:8281.8-8281.48" - cell $and $and$ls180.v:8281$2753 + cell $and $and$ls180.v:8281$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8281$2752_Y + connect \A $not$ls180.v:8281$2754_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8281$2753_Y + connect \Y $and$ls180.v:8281$2755_Y end attribute \src "ls180.v:8314.7-8314.57" - cell $and $and$ls180.v:8314$2759 + cell $and $and$ls180.v:8314$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8314$2758_Y + connect \A $not$ls180.v:8314$2760_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8314$2759_Y + connect \Y $and$ls180.v:8314$2761_Y end attribute \src "ls180.v:8321.7-8321.57" - cell $and $and$ls180.v:8321$2761 + cell $and $and$ls180.v:8321$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8321$2760_Y + connect \A $not$ls180.v:8321$2762_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8321$2761_Y + connect \Y $and$ls180.v:8321$2763_Y end attribute \src "ls180.v:8331.8-8331.75" - cell $and $and$ls180.v:8331$2762 + cell $and $and$ls180.v:8331$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268290,21 +268316,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8331$2762_Y + connect \Y $and$ls180.v:8331$2764_Y end attribute \src "ls180.v:8331.7-8331.107" - cell $and $and$ls180.v:8331$2764 + cell $and $and$ls180.v:8331$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8331$2762_Y - connect \B $not$ls180.v:8331$2763_Y - connect \Y $and$ls180.v:8331$2764_Y + connect \A $and$ls180.v:8331$2764_Y + connect \B $not$ls180.v:8331$2765_Y + connect \Y $and$ls180.v:8331$2766_Y end attribute \src "ls180.v:8337.8-8337.75" - cell $and $and$ls180.v:8337$2767 + cell $and $and$ls180.v:8337$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268312,21 +268338,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8337$2767_Y + connect \Y $and$ls180.v:8337$2769_Y end attribute \src "ls180.v:8337.7-8337.107" - cell $and $and$ls180.v:8337$2769 + cell $and $and$ls180.v:8337$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8337$2767_Y - connect \B $not$ls180.v:8337$2768_Y - connect \Y $and$ls180.v:8337$2769_Y + connect \A $and$ls180.v:8337$2769_Y + connect \B $not$ls180.v:8337$2770_Y + connect \Y $and$ls180.v:8337$2771_Y end attribute \src "ls180.v:8353.8-8353.75" - cell $and $and$ls180.v:8353$2773 + cell $and $and$ls180.v:8353$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268334,21 +268360,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8353$2773_Y + connect \Y $and$ls180.v:8353$2775_Y end attribute \src "ls180.v:8353.7-8353.107" - cell $and $and$ls180.v:8353$2775 + cell $and $and$ls180.v:8353$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8353$2773_Y - connect \B $not$ls180.v:8353$2774_Y - connect \Y $and$ls180.v:8353$2775_Y + connect \A $and$ls180.v:8353$2775_Y + connect \B $not$ls180.v:8353$2776_Y + connect \Y $and$ls180.v:8353$2777_Y end attribute \src "ls180.v:8359.8-8359.75" - cell $and $and$ls180.v:8359$2778 + cell $and $and$ls180.v:8359$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268356,21 +268382,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8359$2778_Y + connect \Y $and$ls180.v:8359$2780_Y end attribute \src "ls180.v:8359.7-8359.107" - cell $and $and$ls180.v:8359$2780 + cell $and $and$ls180.v:8359$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8359$2778_Y - connect \B $not$ls180.v:8359$2779_Y - connect \Y $and$ls180.v:8359$2780_Y + connect \A $and$ls180.v:8359$2780_Y + connect \B $not$ls180.v:8359$2781_Y + connect \Y $and$ls180.v:8359$2782_Y end attribute \src "ls180.v:8507.7-8507.96" - cell $and $and$ls180.v:8507$2808 + cell $and $and$ls180.v:8507$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268378,10 +268404,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8507$2808_Y + connect \Y $and$ls180.v:8507$2810_Y end attribute \src "ls180.v:8508.8-8508.93" - cell $and $and$ls180.v:8508$2809 + cell $and $and$ls180.v:8508$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268389,10 +268415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8508$2809_Y + connect \Y $and$ls180.v:8508$2811_Y end attribute \src "ls180.v:8516.8-8516.93" - cell $and $and$ls180.v:8516$2810 + cell $and $and$ls180.v:8516$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268400,10 +268426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8516$2810_Y + connect \Y $and$ls180.v:8516$2812_Y end attribute \src "ls180.v:8588.7-8588.98" - cell $and $and$ls180.v:8588$2820 + cell $and $and$ls180.v:8588$2822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268411,10 +268437,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8588$2820_Y + connect \Y $and$ls180.v:8588$2822_Y end attribute \src "ls180.v:8589.8-8589.95" - cell $and $and$ls180.v:8589$2821 + cell $and $and$ls180.v:8589$2823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268422,10 +268448,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8589$2821_Y + connect \Y $and$ls180.v:8589$2823_Y end attribute \src "ls180.v:8597.8-8597.95" - cell $and $and$ls180.v:8597$2822 + cell $and $and$ls180.v:8597$2824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268433,10 +268459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8597$2822_Y + connect \Y $and$ls180.v:8597$2824_Y end attribute \src "ls180.v:8667.7-8667.100" - cell $and $and$ls180.v:8667$2832 + cell $and $and$ls180.v:8667$2834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268444,10 +268470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8667$2832_Y + connect \Y $and$ls180.v:8667$2834_Y end attribute \src "ls180.v:8668.8-8668.97" - cell $and $and$ls180.v:8668$2833 + cell $and $and$ls180.v:8668$2835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268455,10 +268481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8668$2833_Y + connect \Y $and$ls180.v:8668$2835_Y end attribute \src "ls180.v:8676.8-8676.97" - cell $and $and$ls180.v:8676$2834 + cell $and $and$ls180.v:8676$2836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268466,10 +268492,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8676$2834_Y + connect \Y $and$ls180.v:8676$2836_Y end attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2840 + cell $and $and$ls180.v:8767$2842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268477,10 +268503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2840_Y + connect \Y $and$ls180.v:8767$2842_Y end attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2841 + cell $and $and$ls180.v:8770$2843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268488,10 +268514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2841_Y + connect \Y $and$ls180.v:8770$2843_Y end attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2842 + cell $and $and$ls180.v:8773$2844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268499,10 +268525,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2842_Y + connect \Y $and$ls180.v:8773$2844_Y end attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2843 + cell $and $and$ls180.v:8776$2845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268510,10 +268536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8776$2843_Y + connect \Y $and$ls180.v:8776$2845_Y end attribute \src "ls180.v:8779.7-8779.82" - cell $and $and$ls180.v:8779$2844 + cell $and $and$ls180.v:8779$2846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268521,10 +268547,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8779$2844_Y + connect \Y $and$ls180.v:8779$2846_Y end attribute \src "ls180.v:8784.7-8784.82" - cell $and $and$ls180.v:8784$2845 + cell $and $and$ls180.v:8784$2847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268532,10 +268558,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8784$2845_Y + connect \Y $and$ls180.v:8784$2847_Y end attribute \src "ls180.v:8789.7-8789.82" - cell $and $and$ls180.v:8789$2846 + cell $and $and$ls180.v:8789$2848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268543,10 +268569,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8789$2846_Y + connect \Y $and$ls180.v:8789$2848_Y end attribute \src "ls180.v:8794.7-8794.82" - cell $and $and$ls180.v:8794$2847 + cell $and $and$ls180.v:8794$2849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268554,10 +268580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8794$2847_Y + connect \Y $and$ls180.v:8794$2849_Y end attribute \src "ls180.v:8799.7-8799.82" - cell $and $and$ls180.v:8799$2848 + cell $and $and$ls180.v:8799$2850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268565,10 +268591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8799$2848_Y + connect \Y $and$ls180.v:8799$2850_Y end attribute \src "ls180.v:8864.8-8864.83" - cell $and $and$ls180.v:8864$2851 + cell $and $and$ls180.v:8864$2853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268576,21 +268602,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8864$2851_Y + connect \Y $and$ls180.v:8864$2853_Y end attribute \src "ls180.v:8864.7-8864.119" - cell $and $and$ls180.v:8864$2853 + cell $and $and$ls180.v:8864$2855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8864$2851_Y - connect \B $not$ls180.v:8864$2852_Y - connect \Y $and$ls180.v:8864$2853_Y + connect \A $and$ls180.v:8864$2853_Y + connect \B $not$ls180.v:8864$2854_Y + connect \Y $and$ls180.v:8864$2855_Y end attribute \src "ls180.v:8870.8-8870.83" - cell $and $and$ls180.v:8870$2856 + cell $and $and$ls180.v:8870$2858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268598,21 +268624,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8870$2856_Y + connect \Y $and$ls180.v:8870$2858_Y end attribute \src "ls180.v:8870.7-8870.119" - cell $and $and$ls180.v:8870$2858 + cell $and $and$ls180.v:8870$2860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8870$2856_Y - connect \B $not$ls180.v:8870$2857_Y - connect \Y $and$ls180.v:8870$2858_Y + connect \A $and$ls180.v:8870$2858_Y + connect \B $not$ls180.v:8870$2859_Y + connect \Y $and$ls180.v:8870$2860_Y end attribute \src "ls180.v:8890.7-8890.88" - cell $and $and$ls180.v:8890$2865 + cell $and $and$ls180.v:8890$2867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268620,10 +268646,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8890$2865_Y + connect \Y $and$ls180.v:8890$2867_Y end attribute \src "ls180.v:8891.8-8891.85" - cell $and $and$ls180.v:8891$2866 + cell $and $and$ls180.v:8891$2868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268631,10 +268657,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8891$2866_Y + connect \Y $and$ls180.v:8891$2868_Y end attribute \src "ls180.v:8899.8-8899.85" - cell $and $and$ls180.v:8899$2867 + cell $and $and$ls180.v:8899$2869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268642,10 +268668,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8899$2867_Y + connect \Y $and$ls180.v:8899$2869_Y end attribute \src "ls180.v:8955.7-8955.88" - cell $and $and$ls180.v:8955$2871 + cell $and $and$ls180.v:8955$2873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268653,10 +268679,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8955$2871_Y + connect \Y $and$ls180.v:8955$2873_Y end attribute \src "ls180.v:8962.8-8962.83" - cell $and $and$ls180.v:8962$2873 + cell $and $and$ls180.v:8962$2875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268664,21 +268690,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8962$2873_Y + connect \Y $and$ls180.v:8962$2875_Y end attribute \src "ls180.v:8962.7-8962.119" - cell $and $and$ls180.v:8962$2875 + cell $and $and$ls180.v:8962$2877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8962$2873_Y - connect \B $not$ls180.v:8962$2874_Y - connect \Y $and$ls180.v:8962$2875_Y + connect \A $and$ls180.v:8962$2875_Y + connect \B $not$ls180.v:8962$2876_Y + connect \Y $and$ls180.v:8962$2877_Y end attribute \src "ls180.v:8968.8-8968.83" - cell $and $and$ls180.v:8968$2878 + cell $and $and$ls180.v:8968$2880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268686,18 +268712,18 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8968$2878_Y + connect \Y $and$ls180.v:8968$2880_Y end attribute \src "ls180.v:8968.7-8968.119" - cell $and $and$ls180.v:8968$2880 + cell $and $and$ls180.v:8968$2882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8968$2878_Y - connect \B $not$ls180.v:8968$2879_Y - connect \Y $and$ls180.v:8968$2880_Y + connect \A $and$ls180.v:8968$2880_Y + connect \B $not$ls180.v:8968$2881_Y + connect \Y $and$ls180.v:8968$2882_Y end attribute \src "ls180.v:2930.30-2930.76" cell $eq $eq$ls180.v:2930$54 @@ -274266,7 +274292,7 @@ module \ls180 connect \Y $eq$ls180.v:7189$2514_Y end attribute \src "ls180.v:7773.8-7773.38" - cell $eq $eq$ls180.v:7773$2606 + cell $eq $eq$ls180.v:7773$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274274,10 +274300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7773$2606_Y + connect \Y $eq$ls180.v:7773$2608_Y end attribute \src "ls180.v:7820.8-7820.42" - cell $eq $eq$ls180.v:7820$2626 + cell $eq $eq$ls180.v:7820$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274285,10 +274311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7820$2626_Y + connect \Y $eq$ls180.v:7820$2628_Y end attribute \src "ls180.v:7840.38-7840.74" - cell $eq $eq$ls180.v:7840$2629 + cell $eq $eq$ls180.v:7840$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274296,10 +274322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7840$2629_Y + connect \Y $eq$ls180.v:7840$2631_Y end attribute \src "ls180.v:7847.7-7847.43" - cell $eq $eq$ls180.v:7847$2631 + cell $eq $eq$ls180.v:7847$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274307,10 +274333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7847$2631_Y + connect \Y $eq$ls180.v:7847$2633_Y end attribute \src "ls180.v:7854.7-7854.43" - cell $eq $eq$ls180.v:7854$2632 + cell $eq $eq$ls180.v:7854$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274318,10 +274344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7854$2632_Y + connect \Y $eq$ls180.v:7854$2634_Y end attribute \src "ls180.v:7862.7-7862.43" - cell $eq $eq$ls180.v:7862$2633 + cell $eq $eq$ls180.v:7862$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274329,10 +274355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7862$2633_Y + connect \Y $eq$ls180.v:7862$2635_Y end attribute \src "ls180.v:7914.9-7914.54" - cell $eq $eq$ls180.v:7914$2651 + cell $eq $eq$ls180.v:7914$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274340,10 +274366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7914$2651_Y + connect \Y $eq$ls180.v:7914$2653_Y end attribute \src "ls180.v:7960.9-7960.54" - cell $eq $eq$ls180.v:7960$2667 + cell $eq $eq$ls180.v:7960$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274351,10 +274377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7960$2667_Y + connect \Y $eq$ls180.v:7960$2669_Y end attribute \src "ls180.v:8006.9-8006.54" - cell $eq $eq$ls180.v:8006$2683 + cell $eq $eq$ls180.v:8006$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274362,10 +274388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8006$2683_Y + connect \Y $eq$ls180.v:8006$2685_Y end attribute \src "ls180.v:8052.9-8052.54" - cell $eq $eq$ls180.v:8052$2699 + cell $eq $eq$ls180.v:8052$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274373,10 +274399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8052$2699_Y + connect \Y $eq$ls180.v:8052$2701_Y end attribute \src "ls180.v:8202.9-8202.41" - cell $eq $eq$ls180.v:8202$2711 + cell $eq $eq$ls180.v:8202$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274384,10 +274410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8202$2711_Y + connect \Y $eq$ls180.v:8202$2713_Y end attribute \src "ls180.v:8217.9-8217.41" - cell $eq $eq$ls180.v:8217$2714 + cell $eq $eq$ls180.v:8217$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274395,10 +274421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8217$2714_Y + connect \Y $eq$ls180.v:8217$2716_Y end attribute \src "ls180.v:8223.49-8223.82" - cell $eq $eq$ls180.v:8223$2715 + cell $eq $eq$ls180.v:8223$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274406,10 +274432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2715_Y + connect \Y $eq$ls180.v:8223$2717_Y end attribute \src "ls180.v:8223.131-8223.164" - cell $eq $eq$ls180.v:8223$2718 + cell $eq $eq$ls180.v:8223$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274417,10 +274443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2718_Y + connect \Y $eq$ls180.v:8223$2720_Y end attribute \src "ls180.v:8223.213-8223.246" - cell $eq $eq$ls180.v:8223$2721 + cell $eq $eq$ls180.v:8223$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274428,10 +274454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2721_Y + connect \Y $eq$ls180.v:8223$2723_Y end attribute \src "ls180.v:8223.295-8223.328" - cell $eq $eq$ls180.v:8223$2724 + cell $eq $eq$ls180.v:8223$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274439,10 +274465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2724_Y + connect \Y $eq$ls180.v:8223$2726_Y end attribute \src "ls180.v:8224.50-8224.83" - cell $eq $eq$ls180.v:8224$2727 + cell $eq $eq$ls180.v:8224$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274450,10 +274476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2727_Y + connect \Y $eq$ls180.v:8224$2729_Y end attribute \src "ls180.v:8224.132-8224.165" - cell $eq $eq$ls180.v:8224$2730 + cell $eq $eq$ls180.v:8224$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274461,10 +274487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2730_Y + connect \Y $eq$ls180.v:8224$2732_Y end attribute \src "ls180.v:8224.214-8224.247" - cell $eq $eq$ls180.v:8224$2733 + cell $eq $eq$ls180.v:8224$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274472,10 +274498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2733_Y + connect \Y $eq$ls180.v:8224$2735_Y end attribute \src "ls180.v:8224.296-8224.329" - cell $eq $eq$ls180.v:8224$2736 + cell $eq $eq$ls180.v:8224$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274483,10 +274509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2736_Y + connect \Y $eq$ls180.v:8224$2738_Y end attribute \src "ls180.v:8259.9-8259.42" - cell $eq $eq$ls180.v:8259$2748 + cell $eq $eq$ls180.v:8259$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274494,10 +274520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8259$2748_Y + connect \Y $eq$ls180.v:8259$2750_Y end attribute \src "ls180.v:8262.10-8262.43" - cell $eq $eq$ls180.v:8262$2749 + cell $eq $eq$ls180.v:8262$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274505,10 +274531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8262$2749_Y + connect \Y $eq$ls180.v:8262$2751_Y end attribute \src "ls180.v:8288.9-8288.42" - cell $eq $eq$ls180.v:8288$2755 + cell $eq $eq$ls180.v:8288$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274516,10 +274542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8288$2755_Y + connect \Y $eq$ls180.v:8288$2757_Y end attribute \src "ls180.v:8293.10-8293.43" - cell $eq $eq$ls180.v:8293$2756 + cell $eq $eq$ls180.v:8293$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274527,10 +274553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8293$2756_Y + connect \Y $eq$ls180.v:8293$2758_Y end attribute \src "ls180.v:8500.9-8500.53" - cell $eq $eq$ls180.v:8500$2805 + cell $eq $eq$ls180.v:8500$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274538,10 +274564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8500$2805_Y + connect \Y $eq$ls180.v:8500$2807_Y end attribute \src "ls180.v:8581.9-8581.54" - cell $eq $eq$ls180.v:8581$2817 + cell $eq $eq$ls180.v:8581$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274549,10 +274575,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8581$2817_Y + connect \Y $eq$ls180.v:8581$2819_Y end attribute \src "ls180.v:8660.9-8660.55" - cell $eq $eq$ls180.v:8660$2829 + cell $eq $eq$ls180.v:8660$2831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274560,10 +274586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8660$2829_Y + connect \Y $eq$ls180.v:8660$2831_Y end attribute \src "ls180.v:8883.9-8883.49" - cell $eq $eq$ls180.v:8883$2862 + cell $eq $eq$ls180.v:8883$2864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274571,29 +274597,29 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8883$2862_Y + connect \Y $eq$ls180.v:8883$2864_Y end attribute \src "ls180.v:8459.8-8459.54" - cell $ge $ge$ls180.v:8459$2797 + cell $ge $ge$ls180.v:8459$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8459$2796_Y - connect \Y $ge$ls180.v:8459$2797_Y + connect \B $sub$ls180.v:8459$2798_Y + connect \Y $ge$ls180.v:8459$2799_Y end attribute \src "ls180.v:8473.8-8473.54" - cell $ge $ge$ls180.v:8473$2801 + cell $ge $ge$ls180.v:8473$2803 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8473$2800_Y - connect \Y $ge$ls180.v:8473$2801_Y + connect \B $sub$ls180.v:8473$2802_Y + connect \Y $ge$ls180.v:8473$2803_Y end attribute \src "ls180.v:5342.47-5342.83" cell $gt $gt$ls180.v:5342$1064 @@ -274618,7 +274644,7 @@ module \ls180 connect \Y $lt$ls180.v:5348$1067_Y end attribute \src "ls180.v:8454.8-8454.43" - cell $lt $lt$ls180.v:8454$2795 + cell $lt $lt$ls180.v:8454$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274626,10 +274652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8454$2795_Y + connect \Y $lt$ls180.v:8454$2797_Y end attribute \src "ls180.v:8468.8-8468.43" - cell $lt $lt$ls180.v:8468$2799 + cell $lt $lt$ls180.v:8468$2801 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274637,10 +274663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8468$2799_Y + connect \Y $lt$ls180.v:8468$2801_Y end attribute \src "ls180.v:10373.33-10373.36" - cell $memrd $memrd$\mem$ls180.v:10373$2916 + cell $memrd $memrd$\mem$ls180.v:10373$2918 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274649,11 +274675,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10373$2916_DATA + connect \DATA $memrd$\mem$ls180.v:10373$2918_DATA connect \EN 1'x end attribute \src "ls180.v:10401.27-10401.32" - cell $memrd $memrd$\mem_1$ls180.v:10401$2942 + cell $memrd $memrd$\mem_1$ls180.v:10401$2944 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274662,11 +274688,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10401$2942_DATA + connect \DATA $memrd$\mem_1$ls180.v:10401$2944_DATA connect \EN 1'x end attribute \src "ls180.v:10429.27-10429.32" - cell $memrd $memrd$\mem_2$ls180.v:10429$2968 + cell $memrd $memrd$\mem_2$ls180.v:10429$2970 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274675,11 +274701,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_2 connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10429$2968_DATA + connect \DATA $memrd$\mem_2$ls180.v:10429$2970_DATA connect \EN 1'x end attribute \src "ls180.v:10457.27-10457.32" - cell $memrd $memrd$\mem_3$ls180.v:10457$2994 + cell $memrd $memrd$\mem_3$ls180.v:10457$2996 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274688,11 +274714,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_3 connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10457$2994_DATA + connect \DATA $memrd$\mem_3$ls180.v:10457$2996_DATA connect \EN 1'x end attribute \src "ls180.v:10485.27-10485.32" - cell $memrd $memrd$\mem_4$ls180.v:10485$3020 + cell $memrd $memrd$\mem_4$ls180.v:10485$3022 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274701,11 +274727,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_4 connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10485$3020_DATA + connect \DATA $memrd$\mem_4$ls180.v:10485$3022_DATA connect \EN 1'x end attribute \src "ls180.v:10496.12-10496.19" - cell $memrd $memrd$\storage$ls180.v:10496$3025 + cell $memrd $memrd$\storage$ls180.v:10496$3027 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274714,11 +274740,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10496$3025_DATA + connect \DATA $memrd$\storage$ls180.v:10496$3027_DATA connect \EN 1'x end attribute \src "ls180.v:10503.68-10503.75" - cell $memrd $memrd$\storage$ls180.v:10503$3027 + cell $memrd $memrd$\storage$ls180.v:10503$3029 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274727,11 +274753,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10503$3027_DATA + connect \DATA $memrd$\storage$ls180.v:10503$3029_DATA connect \EN 1'x end attribute \src "ls180.v:10510.14-10510.23" - cell $memrd $memrd$\storage_1$ls180.v:10510$3032 + cell $memrd $memrd$\storage_1$ls180.v:10510$3034 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274740,11 +274766,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10510$3032_DATA + connect \DATA $memrd$\storage_1$ls180.v:10510$3034_DATA connect \EN 1'x end attribute \src "ls180.v:10517.68-10517.77" - cell $memrd $memrd$\storage_1$ls180.v:10517$3034 + cell $memrd $memrd$\storage_1$ls180.v:10517$3036 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274753,11 +274779,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10517$3034_DATA + connect \DATA $memrd$\storage_1$ls180.v:10517$3036_DATA connect \EN 1'x end attribute \src "ls180.v:10524.14-10524.23" - cell $memrd $memrd$\storage_2$ls180.v:10524$3039 + cell $memrd $memrd$\storage_2$ls180.v:10524$3041 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274766,11 +274792,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10524$3039_DATA + connect \DATA $memrd$\storage_2$ls180.v:10524$3041_DATA connect \EN 1'x end attribute \src "ls180.v:10531.68-10531.77" - cell $memrd $memrd$\storage_2$ls180.v:10531$3041 + cell $memrd $memrd$\storage_2$ls180.v:10531$3043 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274779,11 +274805,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10531$3041_DATA + connect \DATA $memrd$\storage_2$ls180.v:10531$3043_DATA connect \EN 1'x end attribute \src "ls180.v:10538.14-10538.23" - cell $memrd $memrd$\storage_3$ls180.v:10538$3046 + cell $memrd $memrd$\storage_3$ls180.v:10538$3048 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274792,11 +274818,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10538$3046_DATA + connect \DATA $memrd$\storage_3$ls180.v:10538$3048_DATA connect \EN 1'x end attribute \src "ls180.v:10545.68-10545.77" - cell $memrd $memrd$\storage_3$ls180.v:10545$3048 + cell $memrd $memrd$\storage_3$ls180.v:10545$3050 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274805,11 +274831,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10545$3048_DATA + connect \DATA $memrd$\storage_3$ls180.v:10545$3050_DATA connect \EN 1'x end attribute \src "ls180.v:10553.14-10553.23" - cell $memrd $memrd$\storage_4$ls180.v:10553$3053 + cell $memrd $memrd$\storage_4$ls180.v:10553$3055 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274818,11 +274844,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10553$3053_DATA + connect \DATA $memrd$\storage_4$ls180.v:10553$3055_DATA connect \EN 1'x end attribute \src "ls180.v:10558.15-10558.24" - cell $memrd $memrd$\storage_4$ls180.v:10558$3055 + cell $memrd $memrd$\storage_4$ls180.v:10558$3057 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274831,11 +274857,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10558$3055_DATA + connect \DATA $memrd$\storage_4$ls180.v:10558$3057_DATA connect \EN 1'x end attribute \src "ls180.v:10570.14-10570.23" - cell $memrd $memrd$\storage_5$ls180.v:10570$3060 + cell $memrd $memrd$\storage_5$ls180.v:10570$3062 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274844,11 +274870,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10570$3060_DATA + connect \DATA $memrd$\storage_5$ls180.v:10570$3062_DATA connect \EN 1'x end attribute \src "ls180.v:10575.15-10575.24" - cell $memrd $memrd$\storage_5$ls180.v:10575$3062 + cell $memrd $memrd$\storage_5$ls180.v:10575$3064 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274857,11 +274883,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10575$3062_DATA + connect \DATA $memrd$\storage_5$ls180.v:10575$3064_DATA connect \EN 1'x end attribute \src "ls180.v:10586.14-10586.23" - cell $memrd $memrd$\storage_6$ls180.v:10586$3067 + cell $memrd $memrd$\storage_6$ls180.v:10586$3069 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274870,11 +274896,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10586$3067_DATA + connect \DATA $memrd$\storage_6$ls180.v:10586$3069_DATA connect \EN 1'x end attribute \src "ls180.v:10593.45-10593.54" - cell $memrd $memrd$\storage_6$ls180.v:10593$3069 + cell $memrd $memrd$\storage_6$ls180.v:10593$3071 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274883,11 +274909,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10593$3069_DATA + connect \DATA $memrd$\storage_6$ls180.v:10593$3071_DATA connect \EN 1'x end attribute \src "ls180.v:10600.14-10600.23" - cell $memrd $memrd$\storage_7$ls180.v:10600$3074 + cell $memrd $memrd$\storage_7$ls180.v:10600$3076 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274896,11 +274922,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10600$3074_DATA + connect \DATA $memrd$\storage_7$ls180.v:10600$3076_DATA connect \EN 1'x end attribute \src "ls180.v:10607.45-10607.54" - cell $memrd $memrd$\storage_7$ls180.v:10607$3076 + cell $memrd $memrd$\storage_7$ls180.v:10607$3078 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274909,16 +274935,16 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10607$3076_DATA + connect \DATA $memrd$\storage_7$ls180.v:10607$3078_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3078 + cell $memwr $memwr$\mem$ls180.v:0$3080 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3078 + parameter \PRIORITY 3080 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR connect \CLK 1'x @@ -274926,12 +274952,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10355$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3079 + cell $memwr $memwr$\mem$ls180.v:0$3081 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3079 + parameter \PRIORITY 3081 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR connect \CLK 1'x @@ -274939,12 +274965,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10357$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3080 + cell $memwr $memwr$\mem$ls180.v:0$3082 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3080 + parameter \PRIORITY 3082 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR connect \CLK 1'x @@ -274952,12 +274978,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10359$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3081 + cell $memwr $memwr$\mem$ls180.v:0$3083 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3081 + parameter \PRIORITY 3083 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR connect \CLK 1'x @@ -274965,12 +274991,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10361$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3082 + cell $memwr $memwr$\mem$ls180.v:0$3084 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3082 + parameter \PRIORITY 3084 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR connect \CLK 1'x @@ -274978,12 +275004,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10363$5_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3083 + cell $memwr $memwr$\mem$ls180.v:0$3085 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3083 + parameter \PRIORITY 3085 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR connect \CLK 1'x @@ -274991,12 +275017,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10365$6_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3084 + cell $memwr $memwr$\mem$ls180.v:0$3086 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3084 + parameter \PRIORITY 3086 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR connect \CLK 1'x @@ -275004,12 +275030,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10367$7_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3085 + cell $memwr $memwr$\mem$ls180.v:0$3087 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3085 + parameter \PRIORITY 3087 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR connect \CLK 1'x @@ -275017,12 +275043,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10369$8_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3086 + cell $memwr $memwr$\mem_1$ls180.v:0$3088 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3086 + parameter \PRIORITY 3088 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR connect \CLK 1'x @@ -275030,12 +275056,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10383$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3087 + cell $memwr $memwr$\mem_1$ls180.v:0$3089 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3087 + parameter \PRIORITY 3089 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR connect \CLK 1'x @@ -275043,12 +275069,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10385$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3088 + cell $memwr $memwr$\mem_1$ls180.v:0$3090 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3088 + parameter \PRIORITY 3090 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR connect \CLK 1'x @@ -275056,12 +275082,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10387$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3089 + cell $memwr $memwr$\mem_1$ls180.v:0$3091 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3089 + parameter \PRIORITY 3091 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR connect \CLK 1'x @@ -275069,12 +275095,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10389$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3090 + cell $memwr $memwr$\mem_1$ls180.v:0$3092 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3090 + parameter \PRIORITY 3092 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR connect \CLK 1'x @@ -275082,12 +275108,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10391$13_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3091 + cell $memwr $memwr$\mem_1$ls180.v:0$3093 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3091 + parameter \PRIORITY 3093 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR connect \CLK 1'x @@ -275095,12 +275121,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10393$14_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3092 + cell $memwr $memwr$\mem_1$ls180.v:0$3094 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3092 + parameter \PRIORITY 3094 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR connect \CLK 1'x @@ -275108,12 +275134,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10395$15_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3093 + cell $memwr $memwr$\mem_1$ls180.v:0$3095 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3093 + parameter \PRIORITY 3095 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR connect \CLK 1'x @@ -275121,12 +275147,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10397$16_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3094 + cell $memwr $memwr$\mem_2$ls180.v:0$3096 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3094 + parameter \PRIORITY 3096 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR connect \CLK 1'x @@ -275134,12 +275160,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10411$17_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3095 + cell $memwr $memwr$\mem_2$ls180.v:0$3097 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3095 + parameter \PRIORITY 3097 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR connect \CLK 1'x @@ -275147,12 +275173,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10413$18_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3096 + cell $memwr $memwr$\mem_2$ls180.v:0$3098 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3096 + parameter \PRIORITY 3098 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR connect \CLK 1'x @@ -275160,12 +275186,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10415$19_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3097 + cell $memwr $memwr$\mem_2$ls180.v:0$3099 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3097 + parameter \PRIORITY 3099 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR connect \CLK 1'x @@ -275173,12 +275199,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10417$20_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3098 + cell $memwr $memwr$\mem_2$ls180.v:0$3100 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3098 + parameter \PRIORITY 3100 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR connect \CLK 1'x @@ -275186,12 +275212,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10419$21_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3099 + cell $memwr $memwr$\mem_2$ls180.v:0$3101 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3099 + parameter \PRIORITY 3101 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR connect \CLK 1'x @@ -275199,12 +275225,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10421$22_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3100 + cell $memwr $memwr$\mem_2$ls180.v:0$3102 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3100 + parameter \PRIORITY 3102 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR connect \CLK 1'x @@ -275212,12 +275238,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10423$23_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3101 + cell $memwr $memwr$\mem_2$ls180.v:0$3103 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3101 + parameter \PRIORITY 3103 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR connect \CLK 1'x @@ -275225,12 +275251,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10425$24_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3102 + cell $memwr $memwr$\mem_3$ls180.v:0$3104 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3102 + parameter \PRIORITY 3104 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR connect \CLK 1'x @@ -275238,12 +275264,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10439$25_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3103 + cell $memwr $memwr$\mem_3$ls180.v:0$3105 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3103 + parameter \PRIORITY 3105 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR connect \CLK 1'x @@ -275251,12 +275277,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10441$26_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3104 + cell $memwr $memwr$\mem_3$ls180.v:0$3106 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3104 + parameter \PRIORITY 3106 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR connect \CLK 1'x @@ -275264,12 +275290,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10443$27_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3105 + cell $memwr $memwr$\mem_3$ls180.v:0$3107 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3105 + parameter \PRIORITY 3107 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR connect \CLK 1'x @@ -275277,12 +275303,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10445$28_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3106 + cell $memwr $memwr$\mem_3$ls180.v:0$3108 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3106 + parameter \PRIORITY 3108 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR connect \CLK 1'x @@ -275290,12 +275316,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10447$29_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3107 + cell $memwr $memwr$\mem_3$ls180.v:0$3109 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3107 + parameter \PRIORITY 3109 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR connect \CLK 1'x @@ -275303,12 +275329,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10449$30_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3108 + cell $memwr $memwr$\mem_3$ls180.v:0$3110 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3108 + parameter \PRIORITY 3110 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR connect \CLK 1'x @@ -275316,12 +275342,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10451$31_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3109 + cell $memwr $memwr$\mem_3$ls180.v:0$3111 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3109 + parameter \PRIORITY 3111 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR connect \CLK 1'x @@ -275329,12 +275355,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10453$32_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3110 + cell $memwr $memwr$\mem_4$ls180.v:0$3112 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3110 + parameter \PRIORITY 3112 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR connect \CLK 1'x @@ -275342,12 +275368,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10467$33_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3111 + cell $memwr $memwr$\mem_4$ls180.v:0$3113 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3111 + parameter \PRIORITY 3113 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR connect \CLK 1'x @@ -275355,12 +275381,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10469$34_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3112 + cell $memwr $memwr$\mem_4$ls180.v:0$3114 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3112 + parameter \PRIORITY 3114 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR connect \CLK 1'x @@ -275368,12 +275394,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10471$35_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3113 + cell $memwr $memwr$\mem_4$ls180.v:0$3115 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3113 + parameter \PRIORITY 3115 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR connect \CLK 1'x @@ -275381,12 +275407,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10473$36_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3114 + cell $memwr $memwr$\mem_4$ls180.v:0$3116 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3114 + parameter \PRIORITY 3116 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR connect \CLK 1'x @@ -275394,12 +275420,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10475$37_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3115 + cell $memwr $memwr$\mem_4$ls180.v:0$3117 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3115 + parameter \PRIORITY 3117 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR connect \CLK 1'x @@ -275407,12 +275433,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10477$38_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3116 + cell $memwr $memwr$\mem_4$ls180.v:0$3118 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3116 + parameter \PRIORITY 3118 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR connect \CLK 1'x @@ -275420,12 +275446,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10479$39_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3117 + cell $memwr $memwr$\mem_4$ls180.v:0$3119 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3117 + parameter \PRIORITY 3119 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR connect \CLK 1'x @@ -275433,12 +275459,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10481$40_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$3118 + cell $memwr $memwr$\storage$ls180.v:0$3120 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 3118 + parameter \PRIORITY 3120 parameter \WIDTH 25 connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR connect \CLK 1'x @@ -275446,12 +275472,12 @@ module \ls180 connect \EN $memwr$\storage$ls180.v:10495$41_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$3119 + cell $memwr $memwr$\storage_1$ls180.v:0$3121 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 3119 + parameter \PRIORITY 3121 parameter \WIDTH 25 connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR connect \CLK 1'x @@ -275459,12 +275485,12 @@ module \ls180 connect \EN $memwr$\storage_1$ls180.v:10509$42_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$3120 + cell $memwr $memwr$\storage_2$ls180.v:0$3122 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 3120 + parameter \PRIORITY 3122 parameter \WIDTH 25 connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR connect \CLK 1'x @@ -275472,12 +275498,12 @@ module \ls180 connect \EN $memwr$\storage_2$ls180.v:10523$43_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$3121 + cell $memwr $memwr$\storage_3$ls180.v:0$3123 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 3121 + parameter \PRIORITY 3123 parameter \WIDTH 25 connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR connect \CLK 1'x @@ -275485,12 +275511,12 @@ module \ls180 connect \EN $memwr$\storage_3$ls180.v:10537$44_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$3122 + cell $memwr $memwr$\storage_4$ls180.v:0$3124 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 3122 + parameter \PRIORITY 3124 parameter \WIDTH 10 connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR connect \CLK 1'x @@ -275498,12 +275524,12 @@ module \ls180 connect \EN $memwr$\storage_4$ls180.v:10552$45_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$3123 + cell $memwr $memwr$\storage_5$ls180.v:0$3125 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 3123 + parameter \PRIORITY 3125 parameter \WIDTH 10 connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR connect \CLK 1'x @@ -275511,12 +275537,12 @@ module \ls180 connect \EN $memwr$\storage_5$ls180.v:10569$46_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$3124 + cell $memwr $memwr$\storage_6$ls180.v:0$3126 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 3124 + parameter \PRIORITY 3126 parameter \WIDTH 10 connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR connect \CLK 1'x @@ -275524,12 +275550,12 @@ module \ls180 connect \EN $memwr$\storage_6$ls180.v:10585$47_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$3125 + cell $memwr $memwr$\storage_7$ls180.v:0$3127 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 3125 + parameter \PRIORITY 3127 parameter \WIDTH 10 connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR connect \CLK 1'x @@ -275812,7 +275838,7 @@ module \ls180 connect \Y $ne$ls180.v:5878$1177_Y end attribute \src "ls180.v:7763.7-7763.52" - cell $ne $ne$ls180.v:7763$2601 + cell $ne $ne$ls180.v:7763$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275820,10 +275846,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7763$2601_Y + connect \Y $ne$ls180.v:7763$2603_Y end attribute \src "ls180.v:7829.9-7829.43" - cell $ne $ne$ls180.v:7829$2627 + cell $ne $ne$ls180.v:7829$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275831,10 +275857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7829$2627_Y + connect \Y $ne$ls180.v:7829$2629_Y end attribute \src "ls180.v:7865.8-7865.44" - cell $ne $ne$ls180.v:7865$2634 + cell $ne $ne$ls180.v:7865$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275842,10 +275868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7865$2634_Y + connect \Y $ne$ls180.v:7865$2636_Y end attribute \src "ls180.v:8803.9-8803.47" - cell $ne $ne$ls180.v:8803$2849 + cell $ne $ne$ls180.v:8803$2851 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275853,7 +275879,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8803$2849_Y + connect \Y $ne$ls180.v:8803$2851_Y end attribute \src "ls180.v:2893.33-2893.73" cell $not $not$ls180.v:2893$50 @@ -278032,559 +278058,559 @@ module \ls180 connect \Y $not$ls180.v:7189$2517_Y end attribute \src "ls180.v:7690.18-7690.42" - cell $not $not$ls180.v:7690$2571 + cell $not $not$ls180.v:7690$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7690$2571_Y + connect \Y $not$ls180.v:7690$2573_Y end attribute \src "ls180.v:7769.72-7769.101" - cell $not $not$ls180.v:7769$2604 + cell $not $not$ls180.v:7769$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7769$2604_Y + connect \Y $not$ls180.v:7769$2606_Y end attribute \src "ls180.v:7788.8-7788.38" - cell $not $not$ls180.v:7788$2608 + cell $not $not$ls180.v:7788$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7788$2608_Y + connect \Y $not$ls180.v:7788$2610_Y end attribute \src "ls180.v:7792.70-7792.98" - cell $not $not$ls180.v:7792$2611 + cell $not $not$ls180.v:7792$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7792$2611_Y + connect \Y $not$ls180.v:7792$2613_Y end attribute \src "ls180.v:7796.70-7796.98" - cell $not $not$ls180.v:7796$2614 + cell $not $not$ls180.v:7796$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7796$2614_Y + connect \Y $not$ls180.v:7796$2616_Y end attribute \src "ls180.v:7800.70-7800.98" - cell $not $not$ls180.v:7800$2617 + cell $not $not$ls180.v:7800$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7800$2617_Y + connect \Y $not$ls180.v:7800$2619_Y end attribute \src "ls180.v:7804.70-7804.98" - cell $not $not$ls180.v:7804$2620 + cell $not $not$ls180.v:7804$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7804$2620_Y + connect \Y $not$ls180.v:7804$2622_Y end attribute \src "ls180.v:7812.32-7812.55" - cell $not $not$ls180.v:7812$2622 + cell $not $not$ls180.v:7812$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7812$2622_Y + connect \Y $not$ls180.v:7812$2624_Y end attribute \src "ls180.v:7882.136-7882.189" - cell $not $not$ls180.v:7882$2637 + cell $not $not$ls180.v:7882$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7882$2637_Y + connect \Y $not$ls180.v:7882$2639_Y end attribute \src "ls180.v:7888.136-7888.189" - cell $not $not$ls180.v:7888$2642 + cell $not $not$ls180.v:7888$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7888$2642_Y + connect \Y $not$ls180.v:7888$2644_Y end attribute \src "ls180.v:7889.8-7889.61" - cell $not $not$ls180.v:7889$2644 + cell $not $not$ls180.v:7889$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7889$2644_Y + connect \Y $not$ls180.v:7889$2646_Y end attribute \src "ls180.v:7897.8-7897.56" - cell $not $not$ls180.v:7897$2647 + cell $not $not$ls180.v:7897$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7897$2647_Y + connect \Y $not$ls180.v:7897$2649_Y end attribute \src "ls180.v:7912.8-7912.46" - cell $not $not$ls180.v:7912$2649 + cell $not $not$ls180.v:7912$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7912$2649_Y + connect \Y $not$ls180.v:7912$2651_Y end attribute \src "ls180.v:7928.136-7928.189" - cell $not $not$ls180.v:7928$2653 + cell $not $not$ls180.v:7928$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7928$2653_Y + connect \Y $not$ls180.v:7928$2655_Y end attribute \src "ls180.v:7934.136-7934.189" - cell $not $not$ls180.v:7934$2658 + cell $not $not$ls180.v:7934$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7934$2658_Y + connect \Y $not$ls180.v:7934$2660_Y end attribute \src "ls180.v:7935.8-7935.61" - cell $not $not$ls180.v:7935$2660 + cell $not $not$ls180.v:7935$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7935$2660_Y + connect \Y $not$ls180.v:7935$2662_Y end attribute \src "ls180.v:7943.8-7943.56" - cell $not $not$ls180.v:7943$2663 + cell $not $not$ls180.v:7943$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7943$2663_Y + connect \Y $not$ls180.v:7943$2665_Y end attribute \src "ls180.v:7958.8-7958.46" - cell $not $not$ls180.v:7958$2665 + cell $not $not$ls180.v:7958$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7958$2665_Y + connect \Y $not$ls180.v:7958$2667_Y end attribute \src "ls180.v:7974.136-7974.189" - cell $not $not$ls180.v:7974$2669 + cell $not $not$ls180.v:7974$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7974$2669_Y + connect \Y $not$ls180.v:7974$2671_Y end attribute \src "ls180.v:7980.136-7980.189" - cell $not $not$ls180.v:7980$2674 + cell $not $not$ls180.v:7980$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7980$2674_Y + connect \Y $not$ls180.v:7980$2676_Y end attribute \src "ls180.v:7981.8-7981.61" - cell $not $not$ls180.v:7981$2676 + cell $not $not$ls180.v:7981$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7981$2676_Y + connect \Y $not$ls180.v:7981$2678_Y end attribute \src "ls180.v:7989.8-7989.56" - cell $not $not$ls180.v:7989$2679 + cell $not $not$ls180.v:7989$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7989$2679_Y + connect \Y $not$ls180.v:7989$2681_Y end attribute \src "ls180.v:8004.8-8004.46" - cell $not $not$ls180.v:8004$2681 + cell $not $not$ls180.v:8004$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8004$2681_Y + connect \Y $not$ls180.v:8004$2683_Y end attribute \src "ls180.v:8020.136-8020.189" - cell $not $not$ls180.v:8020$2685 + cell $not $not$ls180.v:8020$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8020$2685_Y + connect \Y $not$ls180.v:8020$2687_Y end attribute \src "ls180.v:8026.136-8026.189" - cell $not $not$ls180.v:8026$2690 + cell $not $not$ls180.v:8026$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8026$2690_Y + connect \Y $not$ls180.v:8026$2692_Y end attribute \src "ls180.v:8027.8-8027.61" - cell $not $not$ls180.v:8027$2692 + cell $not $not$ls180.v:8027$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8027$2692_Y + connect \Y $not$ls180.v:8027$2694_Y end attribute \src "ls180.v:8035.8-8035.56" - cell $not $not$ls180.v:8035$2695 + cell $not $not$ls180.v:8035$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8035$2695_Y + connect \Y $not$ls180.v:8035$2697_Y end attribute \src "ls180.v:8050.8-8050.46" - cell $not $not$ls180.v:8050$2697 + cell $not $not$ls180.v:8050$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8050$2697_Y + connect \Y $not$ls180.v:8050$2699_Y end attribute \src "ls180.v:8058.7-8058.22" - cell $not $not$ls180.v:8058$2700 + cell $not $not$ls180.v:8058$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8058$2700_Y + connect \Y $not$ls180.v:8058$2702_Y end attribute \src "ls180.v:8061.8-8061.29" - cell $not $not$ls180.v:8061$2701 + cell $not $not$ls180.v:8061$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8061$2701_Y + connect \Y $not$ls180.v:8061$2703_Y end attribute \src "ls180.v:8065.7-8065.22" - cell $not $not$ls180.v:8065$2703 + cell $not $not$ls180.v:8065$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8065$2703_Y + connect \Y $not$ls180.v:8065$2705_Y end attribute \src "ls180.v:8068.8-8068.29" - cell $not $not$ls180.v:8068$2704 + cell $not $not$ls180.v:8068$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8068$2704_Y + connect \Y $not$ls180.v:8068$2706_Y end attribute \src "ls180.v:8187.30-8187.60" - cell $not $not$ls180.v:8187$2706 + cell $not $not$ls180.v:8187$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8187$2706_Y + connect \Y $not$ls180.v:8187$2708_Y end attribute \src "ls180.v:8188.30-8188.60" - cell $not $not$ls180.v:8188$2707 + cell $not $not$ls180.v:8188$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8188$2707_Y + connect \Y $not$ls180.v:8188$2709_Y end attribute \src "ls180.v:8189.29-8189.59" - cell $not $not$ls180.v:8189$2708 + cell $not $not$ls180.v:8189$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8189$2708_Y + connect \Y $not$ls180.v:8189$2710_Y end attribute \src "ls180.v:8200.8-8200.33" - cell $not $not$ls180.v:8200$2709 + cell $not $not$ls180.v:8200$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8200$2709_Y + connect \Y $not$ls180.v:8200$2711_Y end attribute \src "ls180.v:8215.8-8215.33" - cell $not $not$ls180.v:8215$2712 + cell $not $not$ls180.v:8215$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8215$2712_Y + connect \Y $not$ls180.v:8215$2714_Y end attribute \src "ls180.v:8251.36-8251.58" - cell $not $not$ls180.v:8251$2742 + cell $not $not$ls180.v:8251$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8251$2742_Y + connect \Y $not$ls180.v:8251$2744_Y end attribute \src "ls180.v:8251.64-8251.89" - cell $not $not$ls180.v:8251$2744 + cell $not $not$ls180.v:8251$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8251$2744_Y + connect \Y $not$ls180.v:8251$2746_Y end attribute \src "ls180.v:8280.7-8280.29" - cell $not $not$ls180.v:8280$2751 + cell $not $not$ls180.v:8280$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8280$2751_Y + connect \Y $not$ls180.v:8280$2753_Y end attribute \src "ls180.v:8281.9-8281.26" - cell $not $not$ls180.v:8281$2752 + cell $not $not$ls180.v:8281$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8281$2752_Y + connect \Y $not$ls180.v:8281$2754_Y end attribute \src "ls180.v:8314.8-8314.29" - cell $not $not$ls180.v:8314$2758 + cell $not $not$ls180.v:8314$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8314$2758_Y + connect \Y $not$ls180.v:8314$2760_Y end attribute \src "ls180.v:8321.8-8321.29" - cell $not $not$ls180.v:8321$2760 + cell $not $not$ls180.v:8321$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8321$2760_Y + connect \Y $not$ls180.v:8321$2762_Y end attribute \src "ls180.v:8331.80-8331.106" - cell $not $not$ls180.v:8331$2763 + cell $not $not$ls180.v:8331$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8331$2763_Y + connect \Y $not$ls180.v:8331$2765_Y end attribute \src "ls180.v:8337.80-8337.106" - cell $not $not$ls180.v:8337$2768 + cell $not $not$ls180.v:8337$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8337$2768_Y + connect \Y $not$ls180.v:8337$2770_Y end attribute \src "ls180.v:8338.8-8338.34" - cell $not $not$ls180.v:8338$2770 + cell $not $not$ls180.v:8338$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8338$2770_Y + connect \Y $not$ls180.v:8338$2772_Y end attribute \src "ls180.v:8353.80-8353.106" - cell $not $not$ls180.v:8353$2774 + cell $not $not$ls180.v:8353$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8353$2774_Y + connect \Y $not$ls180.v:8353$2776_Y end attribute \src "ls180.v:8359.80-8359.106" - cell $not $not$ls180.v:8359$2779 + cell $not $not$ls180.v:8359$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8359$2779_Y + connect \Y $not$ls180.v:8359$2781_Y end attribute \src "ls180.v:8360.8-8360.34" - cell $not $not$ls180.v:8360$2781 + cell $not $not$ls180.v:8360$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8360$2781_Y + connect \Y $not$ls180.v:8360$2783_Y end attribute \src "ls180.v:8391.22-8391.41" - cell $not $not$ls180.v:8391$2785 + cell $not $not$ls180.v:8391$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8391$2785_Y + connect \Y $not$ls180.v:8391$2787_Y end attribute \src "ls180.v:8391.46-8391.73" - cell $not $not$ls180.v:8391$2786 + cell $not $not$ls180.v:8391$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8391$2786_Y + connect \Y $not$ls180.v:8391$2788_Y end attribute \src "ls180.v:8426.22-8426.40" - cell $not $not$ls180.v:8426$2790 + cell $not $not$ls180.v:8426$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8426$2790_Y + connect \Y $not$ls180.v:8426$2792_Y end attribute \src "ls180.v:8426.45-8426.70" - cell $not $not$ls180.v:8426$2791 + cell $not $not$ls180.v:8426$2793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8426$2791_Y + connect \Y $not$ls180.v:8426$2793_Y end attribute \src "ls180.v:8480.7-8480.31" - cell $not $not$ls180.v:8480$2802 + cell $not $not$ls180.v:8480$2804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8480$2802_Y + connect \Y $not$ls180.v:8480$2804_Y end attribute \src "ls180.v:8552.8-8552.46" - cell $not $not$ls180.v:8552$2814 + cell $not $not$ls180.v:8552$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8552$2814_Y + connect \Y $not$ls180.v:8552$2816_Y end attribute \src "ls180.v:8633.8-8633.47" - cell $not $not$ls180.v:8633$2826 + cell $not $not$ls180.v:8633$2828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8633$2826_Y + connect \Y $not$ls180.v:8633$2828_Y end attribute \src "ls180.v:8694.8-8694.48" - cell $not $not$ls180.v:8694$2838 + cell $not $not$ls180.v:8694$2840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8694$2838_Y + connect \Y $not$ls180.v:8694$2840_Y end attribute \src "ls180.v:8864.88-8864.118" - cell $not $not$ls180.v:8864$2852 + cell $not $not$ls180.v:8864$2854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8864$2852_Y + connect \Y $not$ls180.v:8864$2854_Y end attribute \src "ls180.v:8870.88-8870.118" - cell $not $not$ls180.v:8870$2857 + cell $not $not$ls180.v:8870$2859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8870$2857_Y + connect \Y $not$ls180.v:8870$2859_Y end attribute \src "ls180.v:8871.8-8871.38" - cell $not $not$ls180.v:8871$2859 + cell $not $not$ls180.v:8871$2861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8871$2859_Y + connect \Y $not$ls180.v:8871$2861_Y end attribute \src "ls180.v:8962.88-8962.118" - cell $not $not$ls180.v:8962$2874 + cell $not $not$ls180.v:8962$2876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8962$2874_Y + connect \Y $not$ls180.v:8962$2876_Y end attribute \src "ls180.v:8968.88-8968.118" - cell $not $not$ls180.v:8968$2879 + cell $not $not$ls180.v:8968$2881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8968$2879_Y + connect \Y $not$ls180.v:8968$2881_Y end attribute \src "ls180.v:8969.8-8969.38" - cell $not $not$ls180.v:8969$2881 + cell $not $not$ls180.v:8969$2883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8969$2881_Y + connect \Y $not$ls180.v:8969$2883_Y end attribute \src "ls180.v:8989.9-8989.28" - cell $not $not$ls180.v:8989$2884 + cell $not $not$ls180.v:8989$2886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8989$2884_Y + connect \Y $not$ls180.v:8989$2886_Y end attribute \src "ls180.v:9008.9-9008.28" - cell $not $not$ls180.v:9008$2885 + cell $not $not$ls180.v:9008$2887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:9008$2885_Y + connect \Y $not$ls180.v:9008$2887_Y end attribute \src "ls180.v:9027.9-9027.28" - cell $not $not$ls180.v:9027$2886 + cell $not $not$ls180.v:9027$2888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:9027$2886_Y + connect \Y $not$ls180.v:9027$2888_Y end attribute \src "ls180.v:9046.9-9046.28" - cell $not $not$ls180.v:9046$2887 + cell $not $not$ls180.v:9046$2889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:9046$2887_Y + connect \Y $not$ls180.v:9046$2889_Y end attribute \src "ls180.v:9065.9-9065.28" - cell $not $not$ls180.v:9065$2888 + cell $not $not$ls180.v:9065$2890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:9065$2888_Y + connect \Y $not$ls180.v:9065$2890_Y end attribute \src "ls180.v:9086.8-9086.21" - cell $not $not$ls180.v:9086$2889 + cell $not $not$ls180.v:9086$2891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:9086$2889_Y + connect \Y $not$ls180.v:9086$2891_Y end attribute \src "ls180.v:10709.8-10709.51" - cell $or $or$ls180.v:10709$3077 + cell $or $or$ls180.v:10709$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278592,7 +278618,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10709$3077_Y + connect \Y $or$ls180.v:10709$3079_Y end attribute \src "ls180.v:2934.10-2934.71" cell $or $or$ls180.v:2934$57 @@ -280641,7 +280667,7 @@ module \ls180 connect \Y $or$ls180.v:7189$2516_Y end attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2574 + cell $or $or$ls180.v:7706$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280649,10 +280675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2574_Y + connect \Y $or$ls180.v:7706$2576_Y end attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2575 + cell $or $or$ls180.v:7707$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280660,10 +280686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2575_Y + connect \Y $or$ls180.v:7707$2577_Y end attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2576 + cell $or $or$ls180.v:7708$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280671,10 +280697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2576_Y + connect \Y $or$ls180.v:7708$2578_Y end attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2577 + cell $or $or$ls180.v:7709$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280682,10 +280708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2577_Y + connect \Y $or$ls180.v:7709$2579_Y end attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2578 + cell $or $or$ls180.v:7710$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280693,10 +280719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2578_Y + connect \Y $or$ls180.v:7710$2580_Y end attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2579 + cell $or $or$ls180.v:7711$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280704,10 +280730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2579_Y + connect \Y $or$ls180.v:7711$2581_Y end attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2580 + cell $or $or$ls180.v:7712$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280715,10 +280741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2580_Y + connect \Y $or$ls180.v:7712$2582_Y end attribute \src "ls180.v:7713.20-7713.71" - cell $or $or$ls180.v:7713$2581 + cell $or $or$ls180.v:7713$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280726,10 +280752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2581_Y + connect \Y $or$ls180.v:7713$2583_Y end attribute \src "ls180.v:7714.20-7714.71" - cell $or $or$ls180.v:7714$2582 + cell $or $or$ls180.v:7714$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280737,10 +280763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2582_Y + connect \Y $or$ls180.v:7714$2584_Y end attribute \src "ls180.v:7715.20-7715.71" - cell $or $or$ls180.v:7715$2583 + cell $or $or$ls180.v:7715$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280748,10 +280774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2583_Y + connect \Y $or$ls180.v:7715$2585_Y end attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2584 + cell $or $or$ls180.v:7716$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280759,10 +280785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2584_Y + connect \Y $or$ls180.v:7716$2586_Y end attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2585 + cell $or $or$ls180.v:7717$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280770,10 +280796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2585_Y + connect \Y $or$ls180.v:7717$2587_Y end attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2586 + cell $or $or$ls180.v:7718$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280781,10 +280807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2586_Y + connect \Y $or$ls180.v:7718$2588_Y end attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2587 + cell $or $or$ls180.v:7719$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280792,10 +280818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2587_Y + connect \Y $or$ls180.v:7719$2589_Y end attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2588 + cell $or $or$ls180.v:7720$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280803,10 +280829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2588_Y + connect \Y $or$ls180.v:7720$2590_Y end attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2589 + cell $or $or$ls180.v:7721$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280814,10 +280840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2589_Y + connect \Y $or$ls180.v:7721$2591_Y end attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2590 + cell $or $or$ls180.v:7722$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280825,10 +280851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2590_Y + connect \Y $or$ls180.v:7722$2592_Y end attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2591 + cell $or $or$ls180.v:7723$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280836,10 +280862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2591_Y + connect \Y $or$ls180.v:7723$2593_Y end attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2592 + cell $or $or$ls180.v:7724$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280847,10 +280873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2592_Y + connect \Y $or$ls180.v:7724$2594_Y end attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2593 + cell $or $or$ls180.v:7725$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280858,10 +280884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2593_Y + connect \Y $or$ls180.v:7725$2595_Y end attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2594 + cell $or $or$ls180.v:7726$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280869,10 +280895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2594_Y + connect \Y $or$ls180.v:7726$2596_Y end attribute \src "ls180.v:7727.21-7727.73" - cell $or $or$ls180.v:7727$2595 + cell $or $or$ls180.v:7727$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280880,10 +280906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7727$2595_Y + connect \Y $or$ls180.v:7727$2597_Y end attribute \src "ls180.v:7728.21-7728.73" - cell $or $or$ls180.v:7728$2596 + cell $or $or$ls180.v:7728$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280891,10 +280917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7728$2596_Y + connect \Y $or$ls180.v:7728$2598_Y end attribute \src "ls180.v:7729.21-7729.73" - cell $or $or$ls180.v:7729$2597 + cell $or $or$ls180.v:7729$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280902,10 +280928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7729$2597_Y + connect \Y $or$ls180.v:7729$2599_Y end attribute \src "ls180.v:7730.7-7730.68" - cell $or $or$ls180.v:7730$2598 + cell $or $or$ls180.v:7730$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280913,10 +280939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:7730$2598_Y + connect \Y $or$ls180.v:7730$2600_Y end attribute \src "ls180.v:7741.7-7741.68" - cell $or $or$ls180.v:7741$2599 + cell $or $or$ls180.v:7741$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280924,10 +280950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:7741$2599_Y + connect \Y $or$ls180.v:7741$2601_Y end attribute \src "ls180.v:7752.7-7752.50" - cell $or $or$ls180.v:7752$2600 + cell $or $or$ls180.v:7752$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280935,142 +280961,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7752$2600_Y + connect \Y $or$ls180.v:7752$2602_Y end attribute \src "ls180.v:7897.7-7897.107" - cell $or $or$ls180.v:7897$2648 + cell $or $or$ls180.v:7897$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7897$2647_Y + connect \A $not$ls180.v:7897$2649_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7897$2648_Y + connect \Y $or$ls180.v:7897$2650_Y end attribute \src "ls180.v:7943.7-7943.107" - cell $or $or$ls180.v:7943$2664 + cell $or $or$ls180.v:7943$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7943$2663_Y + connect \A $not$ls180.v:7943$2665_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7943$2664_Y + connect \Y $or$ls180.v:7943$2666_Y end attribute \src "ls180.v:7989.7-7989.107" - cell $or $or$ls180.v:7989$2680 + cell $or $or$ls180.v:7989$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7989$2679_Y + connect \A $not$ls180.v:7989$2681_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7989$2680_Y + connect \Y $or$ls180.v:7989$2682_Y end attribute \src "ls180.v:8035.7-8035.107" - cell $or $or$ls180.v:8035$2696 + cell $or $or$ls180.v:8035$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8035$2695_Y + connect \A $not$ls180.v:8035$2697_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8035$2696_Y + connect \Y $or$ls180.v:8035$2698_Y end attribute \src "ls180.v:8223.40-8223.125" - cell $or $or$ls180.v:8223$2717 + cell $or $or$ls180.v:8223$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8223$2716_Y - connect \Y $or$ls180.v:8223$2717_Y + connect \B $and$ls180.v:8223$2718_Y + connect \Y $or$ls180.v:8223$2719_Y end attribute \src "ls180.v:8223.39-8223.207" - cell $or $or$ls180.v:8223$2720 + cell $or $or$ls180.v:8223$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2717_Y - connect \B $and$ls180.v:8223$2719_Y - connect \Y $or$ls180.v:8223$2720_Y + connect \A $or$ls180.v:8223$2719_Y + connect \B $and$ls180.v:8223$2721_Y + connect \Y $or$ls180.v:8223$2722_Y end attribute \src "ls180.v:8223.38-8223.289" - cell $or $or$ls180.v:8223$2723 + cell $or $or$ls180.v:8223$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2720_Y - connect \B $and$ls180.v:8223$2722_Y - connect \Y $or$ls180.v:8223$2723_Y + connect \A $or$ls180.v:8223$2722_Y + connect \B $and$ls180.v:8223$2724_Y + connect \Y $or$ls180.v:8223$2725_Y end attribute \src "ls180.v:8223.37-8223.371" - cell $or $or$ls180.v:8223$2726 + cell $or $or$ls180.v:8223$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2723_Y - connect \B $and$ls180.v:8223$2725_Y - connect \Y $or$ls180.v:8223$2726_Y + connect \A $or$ls180.v:8223$2725_Y + connect \B $and$ls180.v:8223$2727_Y + connect \Y $or$ls180.v:8223$2728_Y end attribute \src "ls180.v:8224.41-8224.126" - cell $or $or$ls180.v:8224$2729 + cell $or $or$ls180.v:8224$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8224$2728_Y - connect \Y $or$ls180.v:8224$2729_Y + connect \B $and$ls180.v:8224$2730_Y + connect \Y $or$ls180.v:8224$2731_Y end attribute \src "ls180.v:8224.40-8224.208" - cell $or $or$ls180.v:8224$2732 + cell $or $or$ls180.v:8224$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2729_Y - connect \B $and$ls180.v:8224$2731_Y - connect \Y $or$ls180.v:8224$2732_Y + connect \A $or$ls180.v:8224$2731_Y + connect \B $and$ls180.v:8224$2733_Y + connect \Y $or$ls180.v:8224$2734_Y end attribute \src "ls180.v:8224.39-8224.290" - cell $or $or$ls180.v:8224$2735 + cell $or $or$ls180.v:8224$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2732_Y - connect \B $and$ls180.v:8224$2734_Y - connect \Y $or$ls180.v:8224$2735_Y + connect \A $or$ls180.v:8224$2734_Y + connect \B $and$ls180.v:8224$2736_Y + connect \Y $or$ls180.v:8224$2737_Y end attribute \src "ls180.v:8224.38-8224.372" - cell $or $or$ls180.v:8224$2738 + cell $or $or$ls180.v:8224$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2735_Y - connect \B $and$ls180.v:8224$2737_Y - connect \Y $or$ls180.v:8224$2738_Y + connect \A $or$ls180.v:8224$2737_Y + connect \B $and$ls180.v:8224$2739_Y + connect \Y $or$ls180.v:8224$2740_Y end attribute \src "ls180.v:8228.7-8228.49" - cell $or $or$ls180.v:8228$2739 + cell $or $or$ls180.v:8228$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281078,32 +281104,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8228$2739_Y + connect \Y $or$ls180.v:8228$2741_Y end attribute \src "ls180.v:8391.21-8391.74" - cell $or $or$ls180.v:8391$2787 + cell $or $or$ls180.v:8391$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8391$2785_Y - connect \B $not$ls180.v:8391$2786_Y - connect \Y $or$ls180.v:8391$2787_Y + connect \A $not$ls180.v:8391$2787_Y + connect \B $not$ls180.v:8391$2788_Y + connect \Y $or$ls180.v:8391$2789_Y end attribute \src "ls180.v:8426.21-8426.71" - cell $or $or$ls180.v:8426$2792 + cell $or $or$ls180.v:8426$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8426$2790_Y - connect \B $not$ls180.v:8426$2791_Y - connect \Y $or$ls180.v:8426$2792_Y + connect \A $not$ls180.v:8426$2792_Y + connect \B $not$ls180.v:8426$2793_Y + connect \Y $or$ls180.v:8426$2794_Y end attribute \src "ls180.v:8494.32-8494.85" - cell $or $or$ls180.v:8494$2804 + cell $or $or$ls180.v:8494$2806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281111,21 +281137,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8494$2804_Y + connect \Y $or$ls180.v:8494$2806_Y end attribute \src "ls180.v:8500.8-8500.97" - cell $or $or$ls180.v:8500$2806 + cell $or $or$ls180.v:8500$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8500$2805_Y + connect \A $eq$ls180.v:8500$2807_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8500$2806_Y + connect \Y $or$ls180.v:8500$2808_Y end attribute \src "ls180.v:8517.52-8517.139" - cell $or $or$ls180.v:8517$2811 + cell $or $or$ls180.v:8517$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281133,10 +281159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8517$2811_Y + connect \Y $or$ls180.v:8517$2813_Y end attribute \src "ls180.v:8518.51-8518.136" - cell $or $or$ls180.v:8518$2812 + cell $or $or$ls180.v:8518$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281144,21 +281170,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8518$2812_Y + connect \Y $or$ls180.v:8518$2814_Y end attribute \src "ls180.v:8552.7-8552.87" - cell $or $or$ls180.v:8552$2815 + cell $or $or$ls180.v:8552$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8552$2814_Y + connect \A $not$ls180.v:8552$2816_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8552$2815_Y + connect \Y $or$ls180.v:8552$2817_Y end attribute \src "ls180.v:8575.33-8575.88" - cell $or $or$ls180.v:8575$2816 + cell $or $or$ls180.v:8575$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281166,21 +281192,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8575$2816_Y + connect \Y $or$ls180.v:8575$2818_Y end attribute \src "ls180.v:8581.8-8581.99" - cell $or $or$ls180.v:8581$2818 + cell $or $or$ls180.v:8581$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8581$2817_Y + connect \A $eq$ls180.v:8581$2819_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8581$2818_Y + connect \Y $or$ls180.v:8581$2820_Y end attribute \src "ls180.v:8598.53-8598.142" - cell $or $or$ls180.v:8598$2823 + cell $or $or$ls180.v:8598$2825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281188,10 +281214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8598$2823_Y + connect \Y $or$ls180.v:8598$2825_Y end attribute \src "ls180.v:8599.52-8599.139" - cell $or $or$ls180.v:8599$2824 + cell $or $or$ls180.v:8599$2826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281199,21 +281225,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8599$2824_Y + connect \Y $or$ls180.v:8599$2826_Y end attribute \src "ls180.v:8633.7-8633.89" - cell $or $or$ls180.v:8633$2827 + cell $or $or$ls180.v:8633$2829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8633$2826_Y + connect \A $not$ls180.v:8633$2828_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8633$2827_Y + connect \Y $or$ls180.v:8633$2829_Y end attribute \src "ls180.v:8654.34-8654.91" - cell $or $or$ls180.v:8654$2828 + cell $or $or$ls180.v:8654$2830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281221,21 +281247,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8654$2828_Y + connect \Y $or$ls180.v:8654$2830_Y end attribute \src "ls180.v:8660.8-8660.101" - cell $or $or$ls180.v:8660$2830 + cell $or $or$ls180.v:8660$2832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8660$2829_Y + connect \A $eq$ls180.v:8660$2831_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8660$2830_Y + connect \Y $or$ls180.v:8660$2832_Y end attribute \src "ls180.v:8677.54-8677.145" - cell $or $or$ls180.v:8677$2835 + cell $or $or$ls180.v:8677$2837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281243,10 +281269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8677$2835_Y + connect \Y $or$ls180.v:8677$2837_Y end attribute \src "ls180.v:8678.53-8678.142" - cell $or $or$ls180.v:8678$2836 + cell $or $or$ls180.v:8678$2838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281254,32 +281280,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8678$2836_Y + connect \Y $or$ls180.v:8678$2838_Y end attribute \src "ls180.v:8694.7-8694.91" - cell $or $or$ls180.v:8694$2839 + cell $or $or$ls180.v:8694$2841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8694$2838_Y + connect \A $not$ls180.v:8694$2840_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8694$2839_Y + connect \Y $or$ls180.v:8694$2841_Y end attribute \src "ls180.v:8883.8-8883.89" - cell $or $or$ls180.v:8883$2863 + cell $or $or$ls180.v:8883$2865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8883$2862_Y + connect \A $eq$ls180.v:8883$2864_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8883$2863_Y + connect \Y $or$ls180.v:8883$2865_Y end attribute \src "ls180.v:8900.48-8900.127" - cell $or $or$ls180.v:8900$2868 + cell $or $or$ls180.v:8900$2870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281287,10 +281313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8900$2868_Y + connect \Y $or$ls180.v:8900$2870_Y end attribute \src "ls180.v:8901.47-8901.124" - cell $or $or$ls180.v:8901$2869 + cell $or $or$ls180.v:8901$2871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281298,7 +281324,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8901$2869_Y + connect \Y $or$ls180.v:8901$2871_Y end attribute \src "ls180.v:3358.46-3358.94" cell $sshl $sshl$ls180.v:3358$231 @@ -281642,7 +281668,7 @@ module \ls180 connect \Y $sub$ls180.v:5836$1169_Y end attribute \src "ls180.v:7776.31-7776.60" - cell $sub $sub$ls180.v:7776$2607 + cell $sub $sub$ls180.v:7776$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281650,10 +281676,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7776$2607_Y + connect \Y $sub$ls180.v:7776$2609_Y end attribute \src "ls180.v:7813.31-7813.61" - cell $sub $sub$ls180.v:7813$2624 + cell $sub $sub$ls180.v:7813$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -281661,10 +281687,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7813$2624_Y + connect \Y $sub$ls180.v:7813$2626_Y end attribute \src "ls180.v:7819.34-7819.67" - cell $sub $sub$ls180.v:7819$2625 + cell $sub $sub$ls180.v:7819$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281672,10 +281698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7819$2625_Y + connect \Y $sub$ls180.v:7819$2627_Y end attribute \src "ls180.v:7830.36-7830.69" - cell $sub $sub$ls180.v:7830$2628 + cell $sub $sub$ls180.v:7830$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281683,10 +281709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7830$2628_Y + connect \Y $sub$ls180.v:7830$2630_Y end attribute \src "ls180.v:7894.59-7894.116" - cell $sub $sub$ls180.v:7894$2646 + cell $sub $sub$ls180.v:7894$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281694,10 +281720,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7894$2646_Y + connect \Y $sub$ls180.v:7894$2648_Y end attribute \src "ls180.v:7913.46-7913.90" - cell $sub $sub$ls180.v:7913$2650 + cell $sub $sub$ls180.v:7913$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281705,10 +281731,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7913$2650_Y + connect \Y $sub$ls180.v:7913$2652_Y end attribute \src "ls180.v:7940.59-7940.116" - cell $sub $sub$ls180.v:7940$2662 + cell $sub $sub$ls180.v:7940$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281716,10 +281742,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7940$2662_Y + connect \Y $sub$ls180.v:7940$2664_Y end attribute \src "ls180.v:7959.46-7959.90" - cell $sub $sub$ls180.v:7959$2666 + cell $sub $sub$ls180.v:7959$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281727,10 +281753,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7959$2666_Y + connect \Y $sub$ls180.v:7959$2668_Y end attribute \src "ls180.v:7986.59-7986.116" - cell $sub $sub$ls180.v:7986$2678 + cell $sub $sub$ls180.v:7986$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281738,10 +281764,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7986$2678_Y + connect \Y $sub$ls180.v:7986$2680_Y end attribute \src "ls180.v:8005.46-8005.90" - cell $sub $sub$ls180.v:8005$2682 + cell $sub $sub$ls180.v:8005$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281749,10 +281775,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8005$2682_Y + connect \Y $sub$ls180.v:8005$2684_Y end attribute \src "ls180.v:8032.59-8032.116" - cell $sub $sub$ls180.v:8032$2694 + cell $sub $sub$ls180.v:8032$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281760,10 +281786,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:8032$2694_Y + connect \Y $sub$ls180.v:8032$2696_Y end attribute \src "ls180.v:8051.46-8051.90" - cell $sub $sub$ls180.v:8051$2698 + cell $sub $sub$ls180.v:8051$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281771,10 +281797,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8051$2698_Y + connect \Y $sub$ls180.v:8051$2700_Y end attribute \src "ls180.v:8062.25-8062.48" - cell $sub $sub$ls180.v:8062$2702 + cell $sub $sub$ls180.v:8062$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281782,10 +281808,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:8062$2702_Y + connect \Y $sub$ls180.v:8062$2704_Y end attribute \src "ls180.v:8069.25-8069.48" - cell $sub $sub$ls180.v:8069$2705 + cell $sub $sub$ls180.v:8069$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281793,10 +281819,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:8069$2705_Y + connect \Y $sub$ls180.v:8069$2707_Y end attribute \src "ls180.v:8201.33-8201.64" - cell $sub $sub$ls180.v:8201$2710 + cell $sub $sub$ls180.v:8201$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281804,10 +281830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8201$2710_Y + connect \Y $sub$ls180.v:8201$2712_Y end attribute \src "ls180.v:8216.33-8216.64" - cell $sub $sub$ls180.v:8216$2713 + cell $sub $sub$ls180.v:8216$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281815,10 +281841,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8216$2713_Y + connect \Y $sub$ls180.v:8216$2715_Y end attribute \src "ls180.v:8343.33-8343.64" - cell $sub $sub$ls180.v:8343$2772 + cell $sub $sub$ls180.v:8343$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281826,10 +281852,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8343$2772_Y + connect \Y $sub$ls180.v:8343$2774_Y end attribute \src "ls180.v:8365.33-8365.64" - cell $sub $sub$ls180.v:8365$2783 + cell $sub $sub$ls180.v:8365$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281837,10 +281863,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8365$2783_Y + connect \Y $sub$ls180.v:8365$2785_Y end attribute \src "ls180.v:8400.34-8400.66" - cell $sub $sub$ls180.v:8400$2788 + cell $sub $sub$ls180.v:8400$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281848,10 +281874,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8400$2788_Y + connect \Y $sub$ls180.v:8400$2790_Y end attribute \src "ls180.v:8435.32-8435.62" - cell $sub $sub$ls180.v:8435$2793 + cell $sub $sub$ls180.v:8435$2795 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281859,10 +281885,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8435$2793_Y + connect \Y $sub$ls180.v:8435$2795_Y end attribute \src "ls180.v:8459.30-8459.53" - cell $sub $sub$ls180.v:8459$2796 + cell $sub $sub$ls180.v:8459$2798 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281870,10 +281896,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8459$2796_Y + connect \Y $sub$ls180.v:8459$2798_Y end attribute \src "ls180.v:8473.30-8473.53" - cell $sub $sub$ls180.v:8473$2800 + cell $sub $sub$ls180.v:8473$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281881,10 +281907,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8473$2800_Y + connect \Y $sub$ls180.v:8473$2802_Y end attribute \src "ls180.v:8876.36-8876.70" - cell $sub $sub$ls180.v:8876$2861 + cell $sub $sub$ls180.v:8876$2863 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281892,10 +281918,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8876$2861_Y + connect \Y $sub$ls180.v:8876$2863_Y end attribute \src "ls180.v:8974.36-8974.70" - cell $sub $sub$ls180.v:8974$2883 + cell $sub $sub$ls180.v:8974$2885 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281903,10 +281929,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8974$2883_Y + connect \Y $sub$ls180.v:8974$2885_Y end attribute \src "ls180.v:9087.22-9087.42" - cell $sub $sub$ls180.v:9087$2890 + cell $sub $sub$ls180.v:9087$2892 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -281914,7 +281940,7 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:9087$2890_Y + connect \Y $sub$ls180.v:9087$2892_Y end attribute \src "ls180.v:5113.353-5113.425" cell $xor $xor$ls180.v:5113$860 @@ -284313,7 +284339,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10709$3077_Y + connect \rst $or$ls180.v:10709$3079_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -284526,32 +284552,32 @@ module \ls180 connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4091 + process $proc$ls180.v:0$4093 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4092 + process $proc$ls180.v:0$4094 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4093 + process $proc$ls180.v:0$4095 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4094 + process $proc$ls180.v:0$4096 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4095 + process $proc$ls180.v:0$4097 sync always sync init end attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$3144 + process $proc$ls180.v:100$3146 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always @@ -284559,7 +284585,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$3145 + process $proc$ls180.v:101$3147 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 sync always @@ -284567,7 +284593,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] end attribute \src "ls180.v:1012.5-1012.40" - process $proc$ls180.v:1012$3483 + process $proc$ls180.v:1012$3485 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always @@ -284575,7 +284601,7 @@ module \ls180 sync init end attribute \src "ls180.v:1013.5-1013.39" - process $proc$ls180.v:1013$3484 + process $proc$ls180.v:1013$3486 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always @@ -284583,7 +284609,7 @@ module \ls180 sync init end attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$3146 + process $proc$ls180.v:102$3148 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 sync always @@ -284591,7 +284617,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] end attribute \src "ls180.v:1021.5-1021.38" - process $proc$ls180.v:1021$3485 + process $proc$ls180.v:1021$3487 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always @@ -284599,7 +284625,7 @@ module \ls180 update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end attribute \src "ls180.v:1028.11-1028.42" - process $proc$ls180.v:1028$3486 + process $proc$ls180.v:1028$3488 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always @@ -284607,7 +284633,7 @@ module \ls180 update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end attribute \src "ls180.v:1029.5-1029.37" - process $proc$ls180.v:1029$3487 + process $proc$ls180.v:1029$3489 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always @@ -284615,7 +284641,7 @@ module \ls180 sync init end attribute \src "ls180.v:1030.11-1030.43" - process $proc$ls180.v:1030$3488 + process $proc$ls180.v:1030$3490 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always @@ -284623,7 +284649,7 @@ module \ls180 update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end attribute \src "ls180.v:1031.11-1031.43" - process $proc$ls180.v:1031$3489 + process $proc$ls180.v:1031$3491 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always @@ -284631,7 +284657,7 @@ module \ls180 update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end attribute \src "ls180.v:1032.11-1032.46" - process $proc$ls180.v:1032$3490 + process $proc$ls180.v:1032$3492 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always @@ -284639,7 +284665,7 @@ module \ls180 update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:10353.1-10371.4" - process $proc$ls180.v:10353$2891 + process $proc$ls180.v:10353$2893 assign { } { } assign { } { } assign { } { } @@ -284665,132 +284691,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr[5:0] \main_libresocsim_adr attribute \src "ls180.v:10354.2-10355.65" switch \main_libresocsim_we [0] attribute \src "ls180.v:10354.6-10354.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10356.2-10357.67" switch \main_libresocsim_we [1] attribute \src "ls180.v:10356.6-10356.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10358.2-10359.69" switch \main_libresocsim_we [2] attribute \src "ls180.v:10358.6-10358.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10360.2-10361.69" switch \main_libresocsim_we [3] attribute \src "ls180.v:10360.6-10360.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10362.2-10363.69" switch \main_libresocsim_we [4] attribute \src "ls180.v:10362.6-10362.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10364.2-10365.69" switch \main_libresocsim_we [5] attribute \src "ls180.v:10364.6-10364.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10366.2-10367.69" switch \main_libresocsim_we [6] attribute \src "ls180.v:10366.6-10366.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10368.2-10369.69" switch \main_libresocsim_we [7] attribute \src "ls180.v:10368.6-10368.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 - update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 - update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 - update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 - update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 - update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 - update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 - update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 - update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 - update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 - update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 - update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 - update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 - update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 - update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 - update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 - update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 - update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 - update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 - update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 - update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 - update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 - update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 - update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 + update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 + update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 + update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 + update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 + update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 + update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 + update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 + update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 + update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 + update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 + update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 + update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 + update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 + update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 + update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 + update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 + update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 + update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 + update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 + update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 + update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 + update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 + update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 end attribute \src "ls180.v:10381.1-10399.4" - process $proc$ls180.v:10381$2917 + process $proc$ls180.v:10381$2919 assign { } { } assign { } { } assign { } { } @@ -284816,132 +284842,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_1[5:0] \main_sram0_adr attribute \src "ls180.v:10382.2-10383.55" switch \main_sram0_we [0] attribute \src "ls180.v:10382.6-10382.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10384.2-10385.57" switch \main_sram0_we [1] attribute \src "ls180.v:10384.6-10384.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10386.2-10387.59" switch \main_sram0_we [2] attribute \src "ls180.v:10386.6-10386.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10388.2-10389.59" switch \main_sram0_we [3] attribute \src "ls180.v:10388.6-10388.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10390.2-10391.59" switch \main_sram0_we [4] attribute \src "ls180.v:10390.6-10390.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10392.2-10393.59" switch \main_sram0_we [5] attribute \src "ls180.v:10392.6-10392.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10394.2-10395.59" switch \main_sram0_we [6] attribute \src "ls180.v:10394.6-10394.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10396.2-10397.59" switch \main_sram0_we [7] attribute \src "ls180.v:10396.6-10396.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 - update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 - update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 - update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 - update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 - update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 - update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 - update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 - update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 - update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 - update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 - update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 - update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 - update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 - update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 - update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 - update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 - update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 - update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 - update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 - update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 - update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 - update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 - update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 + update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 + update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 + update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 + update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 + update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 + update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 + update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 + update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 + update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 + update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 + update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 + update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 + update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 + update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 + update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 + update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 + update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 + update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 + update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 + update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 + update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 + update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 + update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 end attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$3147 + process $proc$ls180.v:104$3149 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 sync always @@ -284949,7 +284975,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end attribute \src "ls180.v:10409.1-10427.4" - process $proc$ls180.v:10409$2943 + process $proc$ls180.v:10409$2945 assign { } { } assign { } { } assign { } { } @@ -284975,132 +285001,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_2[5:0] \main_sram1_adr attribute \src "ls180.v:10410.2-10411.55" switch \main_sram1_we [0] attribute \src "ls180.v:10410.6-10410.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10412.2-10413.57" switch \main_sram1_we [1] attribute \src "ls180.v:10412.6-10412.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10414.2-10415.59" switch \main_sram1_we [2] attribute \src "ls180.v:10414.6-10414.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10416.2-10417.59" switch \main_sram1_we [3] attribute \src "ls180.v:10416.6-10416.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10418.2-10419.59" switch \main_sram1_we [4] attribute \src "ls180.v:10418.6-10418.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10420.2-10421.59" switch \main_sram1_we [5] attribute \src "ls180.v:10420.6-10420.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10422.2-10423.59" switch \main_sram1_we [6] attribute \src "ls180.v:10422.6-10422.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10424.2-10425.59" switch \main_sram1_we [7] attribute \src "ls180.v:10424.6-10424.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 - update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 - update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 - update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 - update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 - update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 - update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 - update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 - update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 - update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 - update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 - update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 - update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 - update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 - update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 - update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 - update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 - update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 - update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 - update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 - update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 - update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 - update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 - update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 + update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 + update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 + update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 + update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 + update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 + update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 + update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 + update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 + update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 + update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 + update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 + update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 + update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 + update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 + update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 + update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 + update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 + update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 + update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 + update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 + update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 + update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 + update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 end attribute \src "ls180.v:10437.1-10455.4" - process $proc$ls180.v:10437$2969 + process $proc$ls180.v:10437$2971 assign { } { } assign { } { } assign { } { } @@ -285126,132 +285152,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_3[5:0] \main_sram2_adr attribute \src "ls180.v:10438.2-10439.55" switch \main_sram2_we [0] attribute \src "ls180.v:10438.6-10438.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10440.2-10441.57" switch \main_sram2_we [1] attribute \src "ls180.v:10440.6-10440.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10442.2-10443.59" switch \main_sram2_we [2] attribute \src "ls180.v:10442.6-10442.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10444.2-10445.59" switch \main_sram2_we [3] attribute \src "ls180.v:10444.6-10444.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10446.2-10447.59" switch \main_sram2_we [4] attribute \src "ls180.v:10446.6-10446.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10448.2-10449.59" switch \main_sram2_we [5] attribute \src "ls180.v:10448.6-10448.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10450.2-10451.59" switch \main_sram2_we [6] attribute \src "ls180.v:10450.6-10450.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10452.2-10453.59" switch \main_sram2_we [7] attribute \src "ls180.v:10452.6-10452.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 - update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 - update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 - update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 - update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 - update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 - update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 - update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 - update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 - update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 - update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 - update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 - update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 - update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 - update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 - update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 - update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 - update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 - update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 - update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 - update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 - update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 - update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 - update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 + update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 + update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 + update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 + update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 + update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 + update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 + update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 + update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 + update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 + update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 + update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 + update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 + update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 + update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 + update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 + update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 + update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 + update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 + update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 + update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 + update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 + update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 + update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 end attribute \src "ls180.v:10465.1-10483.4" - process $proc$ls180.v:10465$2995 + process $proc$ls180.v:10465$2997 assign { } { } assign { } { } assign { } { } @@ -285277,324 +285303,324 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_4[5:0] \main_sram3_adr attribute \src "ls180.v:10466.2-10467.55" switch \main_sram3_we [0] attribute \src "ls180.v:10466.6-10466.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10468.2-10469.57" switch \main_sram3_we [1] attribute \src "ls180.v:10468.6-10468.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10470.2-10471.59" switch \main_sram3_we [2] attribute \src "ls180.v:10470.6-10470.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10472.2-10473.59" switch \main_sram3_we [3] attribute \src "ls180.v:10472.6-10472.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10474.2-10475.59" switch \main_sram3_we [4] attribute \src "ls180.v:10474.6-10474.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10476.2-10477.59" switch \main_sram3_we [5] attribute \src "ls180.v:10476.6-10476.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10478.2-10479.59" switch \main_sram3_we [6] attribute \src "ls180.v:10478.6-10478.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10480.2-10481.59" switch \main_sram3_we [7] attribute \src "ls180.v:10480.6-10480.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 - update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 - update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 - update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 - update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 - update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 - update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 - update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 - update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 - update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 - update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 - update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 - update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 - update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 - update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 - update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 - update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 - update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 - update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 - update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 - update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 - update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 - update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 - update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 + update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 + update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 + update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 + update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 + update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 + update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 + update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 + update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 + update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 + update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 + update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 + update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 + update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 + update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 + update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 + update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 + update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 + update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 + update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 + update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 + update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 + update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 + update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 end attribute \src "ls180.v:10493.1-10497.4" - process $proc$ls180.v:10493$3021 + process $proc$ls180.v:10493$3023 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 3'xxx - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3025_DATA + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 3'xxx + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3027_DATA attribute \src "ls180.v:10494.2-10495.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10494.6-10494.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 - update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 - update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 + update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 + update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 end attribute \src "ls180.v:10499.1-10500.4" - process $proc$ls180.v:10499$3026 + process $proc$ls180.v:10499$3028 sync posedge \sys_clk_1 end attribute \src "ls180.v:10507.1-10511.4" - process $proc$ls180.v:10507$3028 + process $proc$ls180.v:10507$3030 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 3'xxx - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3032_DATA + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 3'xxx + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3034_DATA attribute \src "ls180.v:10508.2-10509.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10508.6-10508.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 - update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 - update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 + update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 + update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 end attribute \src "ls180.v:10513.1-10514.4" - process $proc$ls180.v:10513$3033 + process $proc$ls180.v:10513$3035 sync posedge \sys_clk_1 end attribute \src "ls180.v:10521.1-10525.4" - process $proc$ls180.v:10521$3035 + process $proc$ls180.v:10521$3037 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 3'xxx - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3039_DATA + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 3'xxx + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3041_DATA attribute \src "ls180.v:10522.2-10523.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10522.6-10522.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 - update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 - update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 + update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 + update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 end attribute \src "ls180.v:10527.1-10528.4" - process $proc$ls180.v:10527$3040 + process $proc$ls180.v:10527$3042 sync posedge \sys_clk_1 end attribute \src "ls180.v:10535.1-10539.4" - process $proc$ls180.v:10535$3042 + process $proc$ls180.v:10535$3044 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 3'xxx - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3046_DATA + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 3'xxx + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3048_DATA attribute \src "ls180.v:10536.2-10537.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10536.6-10536.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 - update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 - update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 + update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 + update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 end attribute \src "ls180.v:10541.1-10542.4" - process $proc$ls180.v:10541$3047 + process $proc$ls180.v:10541$3049 sync posedge \sys_clk_1 end attribute \src "ls180.v:10550.1-10554.4" - process $proc$ls180.v:10550$3049 + process $proc$ls180.v:10550$3051 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3053_DATA + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3055_DATA attribute \src "ls180.v:10551.2-10552.77" switch \main_uart_tx_fifo_wrport_we attribute \src "ls180.v:10551.6-10551.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 - update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 - update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 + update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 + update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 end attribute \src "ls180.v:10556.1-10559.4" - process $proc$ls180.v:10556$3054 + process $proc$ls180.v:10556$3056 assign $0\memdat_5[9:0] \memdat_5 attribute \src "ls180.v:10557.2-10558.55" switch \main_uart_tx_fifo_rdport_re attribute \src "ls180.v:10557.6-10557.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3055_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3057_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end attribute \src "ls180.v:10567.1-10571.4" - process $proc$ls180.v:10567$3056 + process $proc$ls180.v:10567$3058 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3060_DATA + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3062_DATA attribute \src "ls180.v:10568.2-10569.77" switch \main_uart_rx_fifo_wrport_we attribute \src "ls180.v:10568.6-10568.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 - update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 - update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 + update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 + update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 end attribute \src "ls180.v:10573.1-10576.4" - process $proc$ls180.v:10573$3061 + process $proc$ls180.v:10573$3063 assign $0\memdat_7[9:0] \memdat_7 attribute \src "ls180.v:10574.2-10575.55" switch \main_uart_rx_fifo_rdport_re attribute \src "ls180.v:10574.6-10574.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3062_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3064_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end attribute \src "ls180.v:1058.5-1058.38" - process $proc$ls180.v:1058$3491 + process $proc$ls180.v:1058$3493 assign { } { } assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always @@ -285602,65 +285628,65 @@ module \ls180 update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end attribute \src "ls180.v:10583.1-10587.4" - process $proc$ls180.v:10583$3063 + process $proc$ls180.v:10583$3065 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3067_DATA + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3069_DATA attribute \src "ls180.v:10584.2-10585.85" switch \main_sdblock2mem_fifo_wrport_we attribute \src "ls180.v:10584.6-10584.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 - update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 - update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 + update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 + update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 end attribute \src "ls180.v:10589.1-10590.4" - process $proc$ls180.v:10589$3068 + process $proc$ls180.v:10589$3070 sync posedge \sys_clk_1 end attribute \src "ls180.v:10597.1-10601.4" - process $proc$ls180.v:10597$3070 + process $proc$ls180.v:10597$3072 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3074_DATA + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3076_DATA attribute \src "ls180.v:10598.2-10599.85" switch \main_sdmem2block_fifo_wrport_we attribute \src "ls180.v:10598.6-10598.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 - update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 - update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 + update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 + update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 end attribute \src "ls180.v:10603.1-10604.4" - process $proc$ls180.v:10603$3075 + process $proc$ls180.v:10603$3077 sync posedge \sys_clk_1 end attribute \src "ls180.v:1065.11-1065.42" - process $proc$ls180.v:1065$3492 + process $proc$ls180.v:1065$3494 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always @@ -285668,7 +285694,7 @@ module \ls180 update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end attribute \src "ls180.v:1066.5-1066.37" - process $proc$ls180.v:1066$3493 + process $proc$ls180.v:1066$3495 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always @@ -285676,7 +285702,7 @@ module \ls180 sync init end attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3494 + process $proc$ls180.v:1067$3496 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always @@ -285684,7 +285710,7 @@ module \ls180 update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end attribute \src "ls180.v:1068.11-1068.43" - process $proc$ls180.v:1068$3495 + process $proc$ls180.v:1068$3497 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always @@ -285692,7 +285718,7 @@ module \ls180 update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end attribute \src "ls180.v:1069.11-1069.46" - process $proc$ls180.v:1069$3496 + process $proc$ls180.v:1069$3498 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always @@ -285700,7 +285726,7 @@ module \ls180 update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:1084.5-1084.27" - process $proc$ls180.v:1084$3497 + process $proc$ls180.v:1084$3499 assign { } { } assign $0\main_uart_reset[0:0] 1'0 sync always @@ -285708,7 +285734,7 @@ module \ls180 sync init end attribute \src "ls180.v:1085.12-1085.53" - process $proc$ls180.v:1085$3498 + process $proc$ls180.v:1085$3500 assign { } { } assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 sync always @@ -285716,7 +285742,7 @@ module \ls180 sync init end attribute \src "ls180.v:1086.12-1086.49" - process $proc$ls180.v:1086$3499 + process $proc$ls180.v:1086$3501 assign { } { } assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 sync always @@ -285724,7 +285750,7 @@ module \ls180 update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] end attribute \src "ls180.v:1087.12-1087.54" - process $proc$ls180.v:1087$3500 + process $proc$ls180.v:1087$3502 assign { } { } assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 sync always @@ -285732,7 +285758,7 @@ module \ls180 sync init end attribute \src "ls180.v:1091.12-1091.53" - process $proc$ls180.v:1091$3501 + process $proc$ls180.v:1091$3503 assign { } { } assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 sync always @@ -285740,7 +285766,7 @@ module \ls180 update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] end attribute \src "ls180.v:1092.5-1092.40" - process $proc$ls180.v:1092$3502 + process $proc$ls180.v:1092$3504 assign { } { } assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 sync always @@ -285748,7 +285774,7 @@ module \ls180 update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] end attribute \src "ls180.v:1093.12-1093.49" - process $proc$ls180.v:1093$3503 + process $proc$ls180.v:1093$3505 assign { } { } assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 sync always @@ -285756,7 +285782,7 @@ module \ls180 update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] end attribute \src "ls180.v:1095.12-1095.54" - process $proc$ls180.v:1095$3504 + process $proc$ls180.v:1095$3506 assign { } { } assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 sync always @@ -285764,7 +285790,7 @@ module \ls180 update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] end attribute \src "ls180.v:1096.5-1096.41" - process $proc$ls180.v:1096$3505 + process $proc$ls180.v:1096$3507 assign { } { } assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 sync always @@ -285772,7 +285798,7 @@ module \ls180 update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] end attribute \src "ls180.v:1102.5-1102.32" - process $proc$ls180.v:1102$3506 + process $proc$ls180.v:1102$3508 assign { } { } assign $1\main_spimaster2_done[0:0] 1'0 sync always @@ -285780,7 +285806,7 @@ module \ls180 update \main_spimaster2_done $1\main_spimaster2_done[0:0] end attribute \src "ls180.v:1103.5-1103.31" - process $proc$ls180.v:1103$3507 + process $proc$ls180.v:1103$3509 assign { } { } assign $1\main_spimaster3_irq[0:0] 1'0 sync always @@ -285788,7 +285814,7 @@ module \ls180 update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end attribute \src "ls180.v:1105.11-1105.38" - process $proc$ls180.v:1105$3508 + process $proc$ls180.v:1105$3510 assign { } { } assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always @@ -285796,7 +285822,7 @@ module \ls180 update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end attribute \src "ls180.v:1108.12-1108.47" - process $proc$ls180.v:1108$3509 + process $proc$ls180.v:1108$3511 assign { } { } assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always @@ -285804,7 +285830,7 @@ module \ls180 sync init end attribute \src "ls180.v:1109.5-1109.33" - process $proc$ls180.v:1109$3510 + process $proc$ls180.v:1109$3512 assign { } { } assign $1\main_spimaster9_start[0:0] 1'0 sync always @@ -285812,7 +285838,7 @@ module \ls180 update \main_spimaster9_start $1\main_spimaster9_start[0:0] end attribute \src "ls180.v:1111.12-1111.44" - process $proc$ls180.v:1111$3511 + process $proc$ls180.v:1111$3513 assign { } { } assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 sync always @@ -285820,7 +285846,7 @@ module \ls180 update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end attribute \src "ls180.v:1112.5-1112.31" - process $proc$ls180.v:1112$3512 + process $proc$ls180.v:1112$3514 assign { } { } assign $1\main_spimaster12_re[0:0] 1'0 sync always @@ -285828,7 +285854,7 @@ module \ls180 update \main_spimaster12_re $1\main_spimaster12_re[0:0] end attribute \src "ls180.v:1116.11-1116.42" - process $proc$ls180.v:1116$3513 + process $proc$ls180.v:1116$3515 assign { } { } assign $1\main_spimaster16_storage[7:0] 8'00000000 sync always @@ -285836,7 +285862,7 @@ module \ls180 update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end attribute \src "ls180.v:1117.5-1117.31" - process $proc$ls180.v:1117$3514 + process $proc$ls180.v:1117$3516 assign { } { } assign $1\main_spimaster17_re[0:0] 1'0 sync always @@ -285844,7 +285870,7 @@ module \ls180 update \main_spimaster17_re $1\main_spimaster17_re[0:0] end attribute \src "ls180.v:1121.5-1121.36" - process $proc$ls180.v:1121$3515 + process $proc$ls180.v:1121$3517 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always @@ -285852,7 +285878,7 @@ module \ls180 update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end attribute \src "ls180.v:1122.5-1122.31" - process $proc$ls180.v:1122$3516 + process $proc$ls180.v:1122$3518 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always @@ -285860,7 +285886,7 @@ module \ls180 update \main_spimaster22_re $1\main_spimaster22_re[0:0] end attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3517 + process $proc$ls180.v:1123$3519 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always @@ -285868,7 +285894,7 @@ module \ls180 update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3518 + process $proc$ls180.v:1124$3520 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always @@ -285876,7 +285902,7 @@ module \ls180 update \main_spimaster24_re $1\main_spimaster24_re[0:0] end attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3519 + process $proc$ls180.v:1125$3521 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always @@ -285884,7 +285910,7 @@ module \ls180 update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end attribute \src "ls180.v:1126.5-1126.38" - process $proc$ls180.v:1126$3520 + process $proc$ls180.v:1126$3522 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always @@ -285892,7 +285918,7 @@ module \ls180 update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end attribute \src "ls180.v:1127.11-1127.40" - process $proc$ls180.v:1127$3521 + process $proc$ls180.v:1127$3523 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always @@ -285900,7 +285926,7 @@ module \ls180 update \main_spimaster27_count $1\main_spimaster27_count[2:0] end attribute \src "ls180.v:1128.5-1128.39" - process $proc$ls180.v:1128$3522 + process $proc$ls180.v:1128$3524 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always @@ -285908,7 +285934,7 @@ module \ls180 update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end attribute \src "ls180.v:1129.5-1129.39" - process $proc$ls180.v:1129$3523 + process $proc$ls180.v:1129$3525 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always @@ -285916,7 +285942,7 @@ module \ls180 update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end attribute \src "ls180.v:1130.12-1130.48" - process $proc$ls180.v:1130$3524 + process $proc$ls180.v:1130$3526 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always @@ -285924,7 +285950,7 @@ module \ls180 update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end attribute \src "ls180.v:1133.11-1133.44" - process $proc$ls180.v:1133$3525 + process $proc$ls180.v:1133$3527 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always @@ -285932,7 +285958,7 @@ module \ls180 update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end attribute \src "ls180.v:1134.11-1134.43" - process $proc$ls180.v:1134$3526 + process $proc$ls180.v:1134$3528 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always @@ -285940,7 +285966,7 @@ module \ls180 update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end attribute \src "ls180.v:1135.11-1135.44" - process $proc$ls180.v:1135$3527 + process $proc$ls180.v:1135$3529 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always @@ -285948,7 +285974,7 @@ module \ls180 update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end attribute \src "ls180.v:1138.5-1138.32" - process $proc$ls180.v:1138$3528 + process $proc$ls180.v:1138$3530 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always @@ -285956,7 +285982,7 @@ module \ls180 update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end attribute \src "ls180.v:1139.5-1139.30" - process $proc$ls180.v:1139$3529 + process $proc$ls180.v:1139$3531 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always @@ -285964,7 +285990,7 @@ module \ls180 update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$3148 + process $proc$ls180.v:114$3150 assign { } { } assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 sync always @@ -285972,7 +285998,7 @@ module \ls180 sync init end attribute \src "ls180.v:1141.11-1141.37" - process $proc$ls180.v:1141$3530 + process $proc$ls180.v:1141$3532 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always @@ -285980,7 +286006,7 @@ module \ls180 update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end attribute \src "ls180.v:1145.5-1145.33" - process $proc$ls180.v:1145$3531 + process $proc$ls180.v:1145$3533 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always @@ -285988,7 +286014,7 @@ module \ls180 update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end attribute \src "ls180.v:1147.12-1147.50" - process $proc$ls180.v:1147$3532 + process $proc$ls180.v:1147$3534 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always @@ -285996,7 +286022,7 @@ module \ls180 update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end attribute \src "ls180.v:1148.5-1148.37" - process $proc$ls180.v:1148$3533 + process $proc$ls180.v:1148$3535 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always @@ -286004,7 +286030,7 @@ module \ls180 update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$3149 + process $proc$ls180.v:115$3151 assign { } { } assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 sync always @@ -286012,7 +286038,7 @@ module \ls180 sync init end attribute \src "ls180.v:1152.11-1152.45" - process $proc$ls180.v:1152$3534 + process $proc$ls180.v:1152$3536 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always @@ -286020,7 +286046,7 @@ module \ls180 update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end attribute \src "ls180.v:1153.5-1153.34" - process $proc$ls180.v:1153$3535 + process $proc$ls180.v:1153$3537 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always @@ -286028,7 +286054,7 @@ module \ls180 update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end attribute \src "ls180.v:1157.5-1157.37" - process $proc$ls180.v:1157$3536 + process $proc$ls180.v:1157$3538 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always @@ -286036,7 +286062,7 @@ module \ls180 update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end attribute \src "ls180.v:1158.5-1158.32" - process $proc$ls180.v:1158$3537 + process $proc$ls180.v:1158$3539 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always @@ -286044,7 +286070,7 @@ module \ls180 update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end attribute \src "ls180.v:1159.5-1159.43" - process $proc$ls180.v:1159$3538 + process $proc$ls180.v:1159$3540 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always @@ -286052,7 +286078,7 @@ module \ls180 update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end attribute \src "ls180.v:1160.5-1160.38" - process $proc$ls180.v:1160$3539 + process $proc$ls180.v:1160$3541 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always @@ -286060,7 +286086,7 @@ module \ls180 update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3540 + process $proc$ls180.v:1161$3542 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always @@ -286068,7 +286094,7 @@ module \ls180 update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end attribute \src "ls180.v:1162.5-1162.36" - process $proc$ls180.v:1162$3541 + process $proc$ls180.v:1162$3543 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always @@ -286076,7 +286102,7 @@ module \ls180 update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end attribute \src "ls180.v:1163.11-1163.38" - process $proc$ls180.v:1163$3542 + process $proc$ls180.v:1163$3544 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always @@ -286084,7 +286110,7 @@ module \ls180 update \main_spisdcard_count $1\main_spisdcard_count[2:0] end attribute \src "ls180.v:1164.5-1164.37" - process $proc$ls180.v:1164$3543 + process $proc$ls180.v:1164$3545 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always @@ -286092,7 +286118,7 @@ module \ls180 update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end attribute \src "ls180.v:1165.5-1165.37" - process $proc$ls180.v:1165$3544 + process $proc$ls180.v:1165$3546 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always @@ -286100,7 +286126,7 @@ module \ls180 update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end attribute \src "ls180.v:1166.12-1166.47" - process $proc$ls180.v:1166$3545 + process $proc$ls180.v:1166$3547 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always @@ -286108,7 +286134,7 @@ module \ls180 update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end attribute \src "ls180.v:1169.11-1169.42" - process $proc$ls180.v:1169$3546 + process $proc$ls180.v:1169$3548 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always @@ -286116,7 +286142,7 @@ module \ls180 update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end attribute \src "ls180.v:1170.11-1170.41" - process $proc$ls180.v:1170$3547 + process $proc$ls180.v:1170$3549 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always @@ -286124,7 +286150,7 @@ module \ls180 update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end attribute \src "ls180.v:1171.11-1171.42" - process $proc$ls180.v:1171$3548 + process $proc$ls180.v:1171$3550 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always @@ -286132,7 +286158,7 @@ module \ls180 update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end attribute \src "ls180.v:1172.12-1172.45" - process $proc$ls180.v:1172$3549 + process $proc$ls180.v:1172$3551 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always @@ -286140,7 +286166,7 @@ module \ls180 update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end attribute \src "ls180.v:1173.5-1173.30" - process $proc$ls180.v:1173$3550 + process $proc$ls180.v:1173$3552 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always @@ -286148,7 +286174,7 @@ module \ls180 update \main_spimaster1_re $1\main_spimaster1_re[0:0] end attribute \src "ls180.v:1175.12-1175.30" - process $proc$ls180.v:1175$3551 + process $proc$ls180.v:1175$3553 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always @@ -286156,7 +286182,7 @@ module \ls180 update \main_dummy $1\main_dummy[23:0] end attribute \src "ls180.v:1179.12-1179.37" - process $proc$ls180.v:1179$3552 + process $proc$ls180.v:1179$3554 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always @@ -286164,7 +286190,7 @@ module \ls180 update \main_pwm0_counter $1\main_pwm0_counter[31:0] end attribute \src "ls180.v:1180.5-1180.36" - process $proc$ls180.v:1180$3553 + process $proc$ls180.v:1180$3555 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always @@ -286172,7 +286198,7 @@ module \ls180 update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end attribute \src "ls180.v:1181.5-1181.31" - process $proc$ls180.v:1181$3554 + process $proc$ls180.v:1181$3556 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always @@ -286180,7 +286206,7 @@ module \ls180 update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end attribute \src "ls180.v:1182.12-1182.43" - process $proc$ls180.v:1182$3555 + process $proc$ls180.v:1182$3557 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always @@ -286188,7 +286214,7 @@ module \ls180 update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end attribute \src "ls180.v:1183.5-1183.30" - process $proc$ls180.v:1183$3556 + process $proc$ls180.v:1183$3558 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always @@ -286196,7 +286222,7 @@ module \ls180 update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end attribute \src "ls180.v:1184.12-1184.44" - process $proc$ls180.v:1184$3557 + process $proc$ls180.v:1184$3559 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always @@ -286204,7 +286230,7 @@ module \ls180 update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end attribute \src "ls180.v:1185.5-1185.31" - process $proc$ls180.v:1185$3558 + process $proc$ls180.v:1185$3560 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always @@ -286212,7 +286238,7 @@ module \ls180 update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end attribute \src "ls180.v:1189.12-1189.37" - process $proc$ls180.v:1189$3559 + process $proc$ls180.v:1189$3561 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always @@ -286220,7 +286246,7 @@ module \ls180 update \main_pwm1_counter $1\main_pwm1_counter[31:0] end attribute \src "ls180.v:1190.5-1190.36" - process $proc$ls180.v:1190$3560 + process $proc$ls180.v:1190$3562 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always @@ -286228,7 +286254,7 @@ module \ls180 update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end attribute \src "ls180.v:1191.5-1191.31" - process $proc$ls180.v:1191$3561 + process $proc$ls180.v:1191$3563 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always @@ -286236,7 +286262,7 @@ module \ls180 update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end attribute \src "ls180.v:1192.12-1192.43" - process $proc$ls180.v:1192$3562 + process $proc$ls180.v:1192$3564 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always @@ -286244,7 +286270,7 @@ module \ls180 update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end attribute \src "ls180.v:1193.5-1193.30" - process $proc$ls180.v:1193$3563 + process $proc$ls180.v:1193$3565 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always @@ -286252,7 +286278,7 @@ module \ls180 update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end attribute \src "ls180.v:1194.12-1194.44" - process $proc$ls180.v:1194$3564 + process $proc$ls180.v:1194$3566 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always @@ -286260,7 +286286,7 @@ module \ls180 update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end attribute \src "ls180.v:1195.5-1195.31" - process $proc$ls180.v:1195$3565 + process $proc$ls180.v:1195$3567 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always @@ -286268,7 +286294,7 @@ module \ls180 update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end attribute \src "ls180.v:1199.11-1199.34" - process $proc$ls180.v:1199$3566 + process $proc$ls180.v:1199$3568 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always @@ -286276,7 +286302,7 @@ module \ls180 update \main_i2c_storage $1\main_i2c_storage[2:0] end attribute \src "ls180.v:1200.5-1200.23" - process $proc$ls180.v:1200$3567 + process $proc$ls180.v:1200$3569 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always @@ -286284,7 +286310,7 @@ module \ls180 update \main_i2c_re $1\main_i2c_re[0:0] end attribute \src "ls180.v:1206.11-1206.46" - process $proc$ls180.v:1206$3568 + process $proc$ls180.v:1206$3570 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always @@ -286292,7 +286318,7 @@ module \ls180 update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end attribute \src "ls180.v:1207.5-1207.33" - process $proc$ls180.v:1207$3569 + process $proc$ls180.v:1207$3571 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always @@ -286300,7 +286326,7 @@ module \ls180 update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3570 + process $proc$ls180.v:1209$3572 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always @@ -286308,7 +286334,7 @@ module \ls180 update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end attribute \src "ls180.v:1211.11-1211.41" - process $proc$ls180.v:1211$3571 + process $proc$ls180.v:1211$3573 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always @@ -286316,7 +286342,7 @@ module \ls180 update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end attribute \src "ls180.v:1212.5-1212.35" - process $proc$ls180.v:1212$3572 + process $proc$ls180.v:1212$3574 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always @@ -286324,7 +286350,7 @@ module \ls180 update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end attribute \src "ls180.v:1213.5-1213.36" - process $proc$ls180.v:1213$3573 + process $proc$ls180.v:1213$3575 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always @@ -286332,7 +286358,7 @@ module \ls180 update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end attribute \src "ls180.v:1217.5-1217.40" - process $proc$ls180.v:1217$3574 + process $proc$ls180.v:1217$3576 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always @@ -286340,7 +286366,7 @@ module \ls180 sync init end attribute \src "ls180.v:1222.5-1222.48" - process $proc$ls180.v:1222$3575 + process $proc$ls180.v:1222$3577 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always @@ -286348,7 +286374,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3576 + process $proc$ls180.v:1223$3578 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286356,7 +286382,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1224.5-1224.51" - process $proc$ls180.v:1224$3577 + process $proc$ls180.v:1224$3579 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286364,7 +286390,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1225.11-1225.57" - process $proc$ls180.v:1225$3578 + process $proc$ls180.v:1225$3580 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286372,7 +286398,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end attribute \src "ls180.v:1226.5-1226.52" - process $proc$ls180.v:1226$3579 + process $proc$ls180.v:1226$3581 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286380,7 +286406,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end attribute \src "ls180.v:1227.11-1227.39" - process $proc$ls180.v:1227$3580 + process $proc$ls180.v:1227$3582 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always @@ -286388,7 +286414,7 @@ module \ls180 update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end attribute \src "ls180.v:1232.5-1232.48" - process $proc$ls180.v:1232$3581 + process $proc$ls180.v:1232$3583 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always @@ -286396,7 +286422,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1233.5-1233.50" - process $proc$ls180.v:1233$3582 + process $proc$ls180.v:1233$3584 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286404,7 +286430,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1234.5-1234.51" - process $proc$ls180.v:1234$3583 + process $proc$ls180.v:1234$3585 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286412,7 +286438,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1235.11-1235.57" - process $proc$ls180.v:1235$3584 + process $proc$ls180.v:1235$3586 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286420,7 +286446,7 @@ module \ls180 sync init end attribute \src "ls180.v:1236.5-1236.52" - process $proc$ls180.v:1236$3585 + process $proc$ls180.v:1236$3587 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286428,7 +286454,7 @@ module \ls180 sync init end attribute \src "ls180.v:1237.5-1237.38" - process $proc$ls180.v:1237$3586 + process $proc$ls180.v:1237$3588 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always @@ -286436,7 +286462,7 @@ module \ls180 update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end attribute \src "ls180.v:1238.5-1238.38" - process $proc$ls180.v:1238$3587 + process $proc$ls180.v:1238$3589 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always @@ -286444,7 +286470,7 @@ module \ls180 update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end attribute \src "ls180.v:1239.5-1239.37" - process $proc$ls180.v:1239$3588 + process $proc$ls180.v:1239$3590 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always @@ -286452,7 +286478,7 @@ module \ls180 update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end attribute \src "ls180.v:1240.11-1240.51" - process $proc$ls180.v:1240$3589 + process $proc$ls180.v:1240$3591 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always @@ -286460,7 +286486,7 @@ module \ls180 update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end attribute \src "ls180.v:1241.5-1241.32" - process $proc$ls180.v:1241$3590 + process $proc$ls180.v:1241$3592 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always @@ -286468,7 +286494,7 @@ module \ls180 update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end attribute \src "ls180.v:1242.11-1242.39" - process $proc$ls180.v:1242$3591 + process $proc$ls180.v:1242$3593 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always @@ -286476,7 +286502,7 @@ module \ls180 update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end attribute \src "ls180.v:1245.5-1245.49" - process $proc$ls180.v:1245$3592 + process $proc$ls180.v:1245$3594 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always @@ -286484,7 +286510,7 @@ module \ls180 sync init end attribute \src "ls180.v:1246.5-1246.48" - process $proc$ls180.v:1246$3593 + process $proc$ls180.v:1246$3595 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always @@ -286492,7 +286518,7 @@ module \ls180 sync init end attribute \src "ls180.v:1247.5-1247.55" - process $proc$ls180.v:1247$3594 + process $proc$ls180.v:1247$3596 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -286500,7 +286526,7 @@ module \ls180 sync init end attribute \src "ls180.v:1249.5-1249.57" - process $proc$ls180.v:1249$3595 + process $proc$ls180.v:1249$3597 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -286508,7 +286534,7 @@ module \ls180 sync init end attribute \src "ls180.v:1250.5-1250.58" - process $proc$ls180.v:1250$3596 + process $proc$ls180.v:1250$3598 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -286516,7 +286542,7 @@ module \ls180 sync init end attribute \src "ls180.v:1252.11-1252.64" - process $proc$ls180.v:1252$3597 + process $proc$ls180.v:1252$3599 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -286524,7 +286550,7 @@ module \ls180 sync init end attribute \src "ls180.v:1253.5-1253.59" - process $proc$ls180.v:1253$3598 + process $proc$ls180.v:1253$3600 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -286532,7 +286558,7 @@ module \ls180 sync init end attribute \src "ls180.v:1255.5-1255.48" - process $proc$ls180.v:1255$3599 + process $proc$ls180.v:1255$3601 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always @@ -286540,7 +286566,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1256.5-1256.50" - process $proc$ls180.v:1256$3600 + process $proc$ls180.v:1256$3602 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286548,7 +286574,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3601 + process $proc$ls180.v:1257$3603 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286556,7 +286582,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1258.11-1258.57" - process $proc$ls180.v:1258$3602 + process $proc$ls180.v:1258$3604 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286564,7 +286590,7 @@ module \ls180 sync init end attribute \src "ls180.v:1259.5-1259.52" - process $proc$ls180.v:1259$3603 + process $proc$ls180.v:1259$3605 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286572,7 +286598,7 @@ module \ls180 sync init end attribute \src "ls180.v:1260.5-1260.38" - process $proc$ls180.v:1260$3604 + process $proc$ls180.v:1260$3606 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always @@ -286580,7 +286606,7 @@ module \ls180 update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end attribute \src "ls180.v:1261.5-1261.38" - process $proc$ls180.v:1261$3605 + process $proc$ls180.v:1261$3607 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always @@ -286588,7 +286614,7 @@ module \ls180 update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end attribute \src "ls180.v:1262.5-1262.37" - process $proc$ls180.v:1262$3606 + process $proc$ls180.v:1262$3608 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always @@ -286596,7 +286622,7 @@ module \ls180 update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end attribute \src "ls180.v:1263.11-1263.53" - process $proc$ls180.v:1263$3607 + process $proc$ls180.v:1263$3609 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always @@ -286604,7 +286630,7 @@ module \ls180 update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end attribute \src "ls180.v:1264.5-1264.40" - process $proc$ls180.v:1264$3608 + process $proc$ls180.v:1264$3610 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always @@ -286612,7 +286638,7 @@ module \ls180 update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end attribute \src "ls180.v:1265.5-1265.40" - process $proc$ls180.v:1265$3609 + process $proc$ls180.v:1265$3611 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always @@ -286620,7 +286646,7 @@ module \ls180 update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end attribute \src "ls180.v:1266.5-1266.39" - process $proc$ls180.v:1266$3610 + process $proc$ls180.v:1266$3612 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always @@ -286628,7 +286654,7 @@ module \ls180 update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end attribute \src "ls180.v:1267.11-1267.53" - process $proc$ls180.v:1267$3611 + process $proc$ls180.v:1267$3613 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always @@ -286636,7 +286662,7 @@ module \ls180 update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end attribute \src "ls180.v:1268.11-1268.55" - process $proc$ls180.v:1268$3612 + process $proc$ls180.v:1268$3614 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always @@ -286644,7 +286670,7 @@ module \ls180 update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end attribute \src "ls180.v:1269.12-1269.48" - process $proc$ls180.v:1269$3613 + process $proc$ls180.v:1269$3615 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always @@ -286652,7 +286678,7 @@ module \ls180 update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end attribute \src "ls180.v:1270.11-1270.39" - process $proc$ls180.v:1270$3614 + process $proc$ls180.v:1270$3616 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always @@ -286660,7 +286686,7 @@ module \ls180 update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end attribute \src "ls180.v:1272.5-1272.46" - process $proc$ls180.v:1272$3615 + process $proc$ls180.v:1272$3617 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always @@ -286668,7 +286694,7 @@ module \ls180 sync init end attribute \src "ls180.v:1283.5-1283.53" - process $proc$ls180.v:1283$3616 + process $proc$ls180.v:1283$3618 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always @@ -286676,7 +286702,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end attribute \src "ls180.v:1288.5-1288.36" - process $proc$ls180.v:1288$3617 + process $proc$ls180.v:1288$3619 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always @@ -286684,7 +286710,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end attribute \src "ls180.v:1291.5-1291.53" - process $proc$ls180.v:1291$3618 + process $proc$ls180.v:1291$3620 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always @@ -286692,7 +286718,7 @@ module \ls180 sync init end attribute \src "ls180.v:1292.5-1292.52" - process $proc$ls180.v:1292$3619 + process $proc$ls180.v:1292$3621 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always @@ -286700,7 +286726,7 @@ module \ls180 sync init end attribute \src "ls180.v:1296.5-1296.55" - process $proc$ls180.v:1296$3620 + process $proc$ls180.v:1296$3622 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always @@ -286708,7 +286734,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end attribute \src "ls180.v:1297.5-1297.54" - process $proc$ls180.v:1297$3621 + process $proc$ls180.v:1297$3623 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always @@ -286716,7 +286742,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end attribute \src "ls180.v:1298.11-1298.68" - process $proc$ls180.v:1298$3622 + process $proc$ls180.v:1298$3624 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always @@ -286724,7 +286750,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end attribute \src "ls180.v:1299.11-1299.81" - process $proc$ls180.v:1299$3623 + process $proc$ls180.v:1299$3625 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -286732,7 +286758,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1300.11-1300.54" - process $proc$ls180.v:1300$3624 + process $proc$ls180.v:1300$3626 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always @@ -286740,7 +286766,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end attribute \src "ls180.v:1302.5-1302.53" - process $proc$ls180.v:1302$3625 + process $proc$ls180.v:1302$3627 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always @@ -286748,7 +286774,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end attribute \src "ls180.v:1313.5-1313.49" - process $proc$ls180.v:1313$3626 + process $proc$ls180.v:1313$3628 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always @@ -286756,7 +286782,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end attribute \src "ls180.v:1315.5-1315.49" - process $proc$ls180.v:1315$3627 + process $proc$ls180.v:1315$3629 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always @@ -286764,7 +286790,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end attribute \src "ls180.v:1316.5-1316.48" - process $proc$ls180.v:1316$3628 + process $proc$ls180.v:1316$3630 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always @@ -286772,7 +286798,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end attribute \src "ls180.v:1317.11-1317.62" - process $proc$ls180.v:1317$3629 + process $proc$ls180.v:1317$3631 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always @@ -286780,7 +286806,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end attribute \src "ls180.v:1318.5-1318.38" - process $proc$ls180.v:1318$3630 + process $proc$ls180.v:1318$3632 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always @@ -286788,7 +286814,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end attribute \src "ls180.v:1323.5-1323.49" - process $proc$ls180.v:1323$3631 + process $proc$ls180.v:1323$3633 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always @@ -286796,7 +286822,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1324.5-1324.51" - process $proc$ls180.v:1324$3632 + process $proc$ls180.v:1324$3634 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286804,7 +286830,7 @@ module \ls180 sync init end attribute \src "ls180.v:1325.5-1325.52" - process $proc$ls180.v:1325$3633 + process $proc$ls180.v:1325$3635 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286812,7 +286838,7 @@ module \ls180 sync init end attribute \src "ls180.v:1326.11-1326.58" - process $proc$ls180.v:1326$3634 + process $proc$ls180.v:1326$3636 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286820,7 +286846,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end attribute \src "ls180.v:1327.5-1327.53" - process $proc$ls180.v:1327$3635 + process $proc$ls180.v:1327$3637 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286828,7 +286854,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end attribute \src "ls180.v:1328.5-1328.39" - process $proc$ls180.v:1328$3636 + process $proc$ls180.v:1328$3638 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always @@ -286836,7 +286862,7 @@ module \ls180 update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3637 + process $proc$ls180.v:1329$3639 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always @@ -286844,7 +286870,7 @@ module \ls180 update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end attribute \src "ls180.v:1330.5-1330.39" - process $proc$ls180.v:1330$3638 + process $proc$ls180.v:1330$3640 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always @@ -286852,7 +286878,7 @@ module \ls180 update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end attribute \src "ls180.v:1331.5-1331.38" - process $proc$ls180.v:1331$3639 + process $proc$ls180.v:1331$3641 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always @@ -286860,7 +286886,7 @@ module \ls180 update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end attribute \src "ls180.v:1332.11-1332.52" - process $proc$ls180.v:1332$3640 + process $proc$ls180.v:1332$3642 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always @@ -286868,7 +286894,7 @@ module \ls180 update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end attribute \src "ls180.v:1333.5-1333.33" - process $proc$ls180.v:1333$3641 + process $proc$ls180.v:1333$3643 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always @@ -286876,7 +286902,7 @@ module \ls180 update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end attribute \src "ls180.v:1334.11-1334.40" - process $proc$ls180.v:1334$3642 + process $proc$ls180.v:1334$3644 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always @@ -286884,7 +286910,7 @@ module \ls180 update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end attribute \src "ls180.v:1335.5-1335.50" - process $proc$ls180.v:1335$3643 + process $proc$ls180.v:1335$3645 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always @@ -286892,7 +286918,7 @@ module \ls180 sync init end attribute \src "ls180.v:1337.5-1337.50" - process $proc$ls180.v:1337$3644 + process $proc$ls180.v:1337$3646 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always @@ -286900,7 +286926,7 @@ module \ls180 sync init end attribute \src "ls180.v:1338.5-1338.49" - process $proc$ls180.v:1338$3645 + process $proc$ls180.v:1338$3647 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always @@ -286908,7 +286934,7 @@ module \ls180 sync init end attribute \src "ls180.v:1339.5-1339.56" - process $proc$ls180.v:1339$3646 + process $proc$ls180.v:1339$3648 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -286916,7 +286942,7 @@ module \ls180 sync init end attribute \src "ls180.v:1340.5-1340.58" - process $proc$ls180.v:1340$3647 + process $proc$ls180.v:1340$3649 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always @@ -286924,7 +286950,7 @@ module \ls180 sync init end attribute \src "ls180.v:1341.5-1341.58" - process $proc$ls180.v:1341$3648 + process $proc$ls180.v:1341$3650 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -286932,7 +286958,7 @@ module \ls180 sync init end attribute \src "ls180.v:1342.5-1342.59" - process $proc$ls180.v:1342$3649 + process $proc$ls180.v:1342$3651 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -286940,7 +286966,7 @@ module \ls180 sync init end attribute \src "ls180.v:1343.11-1343.65" - process $proc$ls180.v:1343$3650 + process $proc$ls180.v:1343$3652 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always @@ -286948,7 +286974,7 @@ module \ls180 sync init end attribute \src "ls180.v:1344.11-1344.65" - process $proc$ls180.v:1344$3651 + process $proc$ls180.v:1344$3653 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -286956,7 +286982,7 @@ module \ls180 sync init end attribute \src "ls180.v:1345.5-1345.60" - process $proc$ls180.v:1345$3652 + process $proc$ls180.v:1345$3654 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -286964,7 +286990,7 @@ module \ls180 sync init end attribute \src "ls180.v:1346.5-1346.34" - process $proc$ls180.v:1346$3653 + process $proc$ls180.v:1346$3655 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always @@ -286972,7 +286998,7 @@ module \ls180 update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end attribute \src "ls180.v:1347.5-1347.34" - process $proc$ls180.v:1347$3654 + process $proc$ls180.v:1347$3656 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always @@ -286980,7 +287006,7 @@ module \ls180 update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end attribute \src "ls180.v:1348.5-1348.34" - process $proc$ls180.v:1348$3655 + process $proc$ls180.v:1348$3657 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always @@ -286988,7 +287014,7 @@ module \ls180 update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end attribute \src "ls180.v:1350.5-1350.47" - process $proc$ls180.v:1350$3656 + process $proc$ls180.v:1350$3658 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always @@ -286996,7 +287022,7 @@ module \ls180 sync init end attribute \src "ls180.v:1361.5-1361.54" - process $proc$ls180.v:1361$3657 + process $proc$ls180.v:1361$3659 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always @@ -287004,7 +287030,7 @@ module \ls180 update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end attribute \src "ls180.v:1366.5-1366.37" - process $proc$ls180.v:1366$3658 + process $proc$ls180.v:1366$3660 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always @@ -287012,7 +287038,7 @@ module \ls180 update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end attribute \src "ls180.v:1369.5-1369.54" - process $proc$ls180.v:1369$3659 + process $proc$ls180.v:1369$3661 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always @@ -287020,7 +287046,7 @@ module \ls180 sync init end attribute \src "ls180.v:1370.5-1370.53" - process $proc$ls180.v:1370$3660 + process $proc$ls180.v:1370$3662 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always @@ -287028,7 +287054,7 @@ module \ls180 sync init end attribute \src "ls180.v:1374.5-1374.56" - process $proc$ls180.v:1374$3661 + process $proc$ls180.v:1374$3663 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always @@ -287036,7 +287062,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end attribute \src "ls180.v:1375.5-1375.55" - process $proc$ls180.v:1375$3662 + process $proc$ls180.v:1375$3664 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always @@ -287044,7 +287070,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end attribute \src "ls180.v:1376.11-1376.69" - process $proc$ls180.v:1376$3663 + process $proc$ls180.v:1376$3665 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always @@ -287052,7 +287078,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end attribute \src "ls180.v:1377.11-1377.82" - process $proc$ls180.v:1377$3664 + process $proc$ls180.v:1377$3666 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -287060,7 +287086,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1378.11-1378.55" - process $proc$ls180.v:1378$3665 + process $proc$ls180.v:1378$3667 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always @@ -287068,7 +287094,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end attribute \src "ls180.v:1380.5-1380.54" - process $proc$ls180.v:1380$3666 + process $proc$ls180.v:1380$3668 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always @@ -287076,7 +287102,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end attribute \src "ls180.v:1391.5-1391.50" - process $proc$ls180.v:1391$3667 + process $proc$ls180.v:1391$3669 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always @@ -287084,7 +287110,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end attribute \src "ls180.v:1393.5-1393.50" - process $proc$ls180.v:1393$3668 + process $proc$ls180.v:1393$3670 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always @@ -287092,7 +287118,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end attribute \src "ls180.v:1394.5-1394.49" - process $proc$ls180.v:1394$3669 + process $proc$ls180.v:1394$3671 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always @@ -287100,7 +287126,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end attribute \src "ls180.v:1395.11-1395.63" - process $proc$ls180.v:1395$3670 + process $proc$ls180.v:1395$3672 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always @@ -287108,7 +287134,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end attribute \src "ls180.v:1396.5-1396.39" - process $proc$ls180.v:1396$3671 + process $proc$ls180.v:1396$3673 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always @@ -287116,7 +287142,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end attribute \src "ls180.v:1399.5-1399.50" - process $proc$ls180.v:1399$3672 + process $proc$ls180.v:1399$3674 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always @@ -287124,7 +287150,7 @@ module \ls180 sync init end attribute \src "ls180.v:1400.5-1400.49" - process $proc$ls180.v:1400$3673 + process $proc$ls180.v:1400$3675 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always @@ -287132,7 +287158,7 @@ module \ls180 sync init end attribute \src "ls180.v:1401.5-1401.56" - process $proc$ls180.v:1401$3674 + process $proc$ls180.v:1401$3676 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -287140,7 +287166,7 @@ module \ls180 sync init end attribute \src "ls180.v:1403.5-1403.58" - process $proc$ls180.v:1403$3675 + process $proc$ls180.v:1403$3677 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -287148,7 +287174,7 @@ module \ls180 sync init end attribute \src "ls180.v:1404.5-1404.59" - process $proc$ls180.v:1404$3676 + process $proc$ls180.v:1404$3678 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -287156,7 +287182,7 @@ module \ls180 sync init end attribute \src "ls180.v:1406.11-1406.65" - process $proc$ls180.v:1406$3677 + process $proc$ls180.v:1406$3679 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -287164,7 +287190,7 @@ module \ls180 sync init end attribute \src "ls180.v:1407.5-1407.60" - process $proc$ls180.v:1407$3678 + process $proc$ls180.v:1407$3680 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -287172,7 +287198,7 @@ module \ls180 sync init end attribute \src "ls180.v:1409.5-1409.49" - process $proc$ls180.v:1409$3679 + process $proc$ls180.v:1409$3681 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always @@ -287180,7 +287206,7 @@ module \ls180 update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1410.5-1410.51" - process $proc$ls180.v:1410$3680 + process $proc$ls180.v:1410$3682 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -287188,7 +287214,7 @@ module \ls180 sync init end attribute \src "ls180.v:1411.5-1411.52" - process $proc$ls180.v:1411$3681 + process $proc$ls180.v:1411$3683 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -287196,7 +287222,7 @@ module \ls180 sync init end attribute \src "ls180.v:1412.11-1412.58" - process $proc$ls180.v:1412$3682 + process $proc$ls180.v:1412$3684 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -287204,7 +287230,7 @@ module \ls180 sync init end attribute \src "ls180.v:1413.5-1413.53" - process $proc$ls180.v:1413$3683 + process $proc$ls180.v:1413$3685 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -287212,7 +287238,7 @@ module \ls180 sync init end attribute \src "ls180.v:1414.5-1414.39" - process $proc$ls180.v:1414$3684 + process $proc$ls180.v:1414$3686 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always @@ -287220,7 +287246,7 @@ module \ls180 update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end attribute \src "ls180.v:1415.5-1415.39" - process $proc$ls180.v:1415$3685 + process $proc$ls180.v:1415$3687 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always @@ -287228,7 +287254,7 @@ module \ls180 update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end attribute \src "ls180.v:1416.5-1416.38" - process $proc$ls180.v:1416$3686 + process $proc$ls180.v:1416$3688 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always @@ -287236,7 +287262,7 @@ module \ls180 update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end attribute \src "ls180.v:1417.11-1417.61" - process $proc$ls180.v:1417$3687 + process $proc$ls180.v:1417$3689 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always @@ -287244,7 +287270,7 @@ module \ls180 update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end attribute \src "ls180.v:1418.5-1418.41" - process $proc$ls180.v:1418$3688 + process $proc$ls180.v:1418$3690 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always @@ -287252,7 +287278,7 @@ module \ls180 update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end attribute \src "ls180.v:1419.5-1419.41" - process $proc$ls180.v:1419$3689 + process $proc$ls180.v:1419$3691 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always @@ -287260,7 +287286,7 @@ module \ls180 update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end attribute \src "ls180.v:1420.5-1420.41" - process $proc$ls180.v:1420$3690 + process $proc$ls180.v:1420$3692 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always @@ -287268,7 +287294,7 @@ module \ls180 sync init end attribute \src "ls180.v:1421.5-1421.40" - process $proc$ls180.v:1421$3691 + process $proc$ls180.v:1421$3693 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always @@ -287276,7 +287302,7 @@ module \ls180 update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end attribute \src "ls180.v:1422.11-1422.54" - process $proc$ls180.v:1422$3692 + process $proc$ls180.v:1422$3694 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always @@ -287284,7 +287310,7 @@ module \ls180 update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end attribute \src "ls180.v:1423.11-1423.56" - process $proc$ls180.v:1423$3693 + process $proc$ls180.v:1423$3695 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always @@ -287292,7 +287318,7 @@ module \ls180 update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end attribute \src "ls180.v:1424.5-1424.33" - process $proc$ls180.v:1424$3694 + process $proc$ls180.v:1424$3696 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always @@ -287300,7 +287326,7 @@ module \ls180 update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end attribute \src "ls180.v:1425.12-1425.49" - process $proc$ls180.v:1425$3695 + process $proc$ls180.v:1425$3697 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always @@ -287308,7 +287334,7 @@ module \ls180 update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end attribute \src "ls180.v:1426.11-1426.41" - process $proc$ls180.v:1426$3696 + process $proc$ls180.v:1426$3698 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always @@ -287316,7 +287342,7 @@ module \ls180 update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end attribute \src "ls180.v:1428.5-1428.48" - process $proc$ls180.v:1428$3697 + process $proc$ls180.v:1428$3699 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always @@ -287324,7 +287350,7 @@ module \ls180 sync init end attribute \src "ls180.v:1439.5-1439.55" - process $proc$ls180.v:1439$3698 + process $proc$ls180.v:1439$3700 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always @@ -287332,7 +287358,7 @@ module \ls180 update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end attribute \src "ls180.v:1444.5-1444.38" - process $proc$ls180.v:1444$3699 + process $proc$ls180.v:1444$3701 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always @@ -287340,7 +287366,7 @@ module \ls180 update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end attribute \src "ls180.v:1447.5-1447.55" - process $proc$ls180.v:1447$3700 + process $proc$ls180.v:1447$3702 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always @@ -287348,7 +287374,7 @@ module \ls180 sync init end attribute \src "ls180.v:1448.5-1448.54" - process $proc$ls180.v:1448$3701 + process $proc$ls180.v:1448$3703 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always @@ -287356,7 +287382,7 @@ module \ls180 sync init end attribute \src "ls180.v:1452.5-1452.57" - process $proc$ls180.v:1452$3702 + process $proc$ls180.v:1452$3704 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always @@ -287364,7 +287390,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end attribute \src "ls180.v:1453.5-1453.56" - process $proc$ls180.v:1453$3703 + process $proc$ls180.v:1453$3705 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always @@ -287372,7 +287398,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end attribute \src "ls180.v:1454.11-1454.70" - process $proc$ls180.v:1454$3704 + process $proc$ls180.v:1454$3706 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always @@ -287380,7 +287406,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end attribute \src "ls180.v:1455.11-1455.83" - process $proc$ls180.v:1455$3705 + process $proc$ls180.v:1455$3707 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always @@ -287388,7 +287414,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end attribute \src "ls180.v:1456.5-1456.50" - process $proc$ls180.v:1456$3706 + process $proc$ls180.v:1456$3708 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always @@ -287396,7 +287422,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end attribute \src "ls180.v:1458.5-1458.55" - process $proc$ls180.v:1458$3707 + process $proc$ls180.v:1458$3709 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always @@ -287404,7 +287430,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end attribute \src "ls180.v:1469.5-1469.51" - process $proc$ls180.v:1469$3708 + process $proc$ls180.v:1469$3710 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always @@ -287412,7 +287438,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end attribute \src "ls180.v:1471.5-1471.51" - process $proc$ls180.v:1471$3709 + process $proc$ls180.v:1471$3711 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always @@ -287420,7 +287446,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end attribute \src "ls180.v:1472.5-1472.50" - process $proc$ls180.v:1472$3710 + process $proc$ls180.v:1472$3712 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always @@ -287428,7 +287454,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end attribute \src "ls180.v:1473.11-1473.64" - process $proc$ls180.v:1473$3711 + process $proc$ls180.v:1473$3713 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always @@ -287436,7 +287462,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end attribute \src "ls180.v:1474.5-1474.40" - process $proc$ls180.v:1474$3712 + process $proc$ls180.v:1474$3714 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always @@ -287444,7 +287470,7 @@ module \ls180 update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end attribute \src "ls180.v:1476.5-1476.35" - process $proc$ls180.v:1476$3713 + process $proc$ls180.v:1476$3715 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always @@ -287452,7 +287478,7 @@ module \ls180 update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end attribute \src "ls180.v:1479.11-1479.42" - process $proc$ls180.v:1479$3714 + process $proc$ls180.v:1479$3716 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always @@ -287460,7 +287486,7 @@ module \ls180 update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end attribute \src "ls180.v:1492.12-1492.52" - process $proc$ls180.v:1492$3715 + process $proc$ls180.v:1492$3717 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always @@ -287468,7 +287494,7 @@ module \ls180 update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end attribute \src "ls180.v:1493.5-1493.39" - process $proc$ls180.v:1493$3716 + process $proc$ls180.v:1493$3718 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always @@ -287476,7 +287502,7 @@ module \ls180 update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end attribute \src "ls180.v:1494.12-1494.51" - process $proc$ls180.v:1494$3717 + process $proc$ls180.v:1494$3719 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always @@ -287484,7 +287510,7 @@ module \ls180 update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end attribute \src "ls180.v:1495.5-1495.38" - process $proc$ls180.v:1495$3718 + process $proc$ls180.v:1495$3720 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always @@ -287492,7 +287518,7 @@ module \ls180 update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end attribute \src "ls180.v:1499.5-1499.34" - process $proc$ls180.v:1499$3719 + process $proc$ls180.v:1499$3721 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always @@ -287500,7 +287526,7 @@ module \ls180 sync init end attribute \src "ls180.v:1500.13-1500.53" - process $proc$ls180.v:1500$3720 + process $proc$ls180.v:1500$3722 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always @@ -287508,7 +287534,7 @@ module \ls180 update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end attribute \src "ls180.v:1506.11-1506.51" - process $proc$ls180.v:1506$3721 + process $proc$ls180.v:1506$3723 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always @@ -287516,7 +287542,7 @@ module \ls180 update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end attribute \src "ls180.v:1507.5-1507.39" - process $proc$ls180.v:1507$3722 + process $proc$ls180.v:1507$3724 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always @@ -287524,7 +287550,7 @@ module \ls180 update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end attribute \src "ls180.v:1508.12-1508.51" - process $proc$ls180.v:1508$3723 + process $proc$ls180.v:1508$3725 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always @@ -287532,7 +287558,7 @@ module \ls180 update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end attribute \src "ls180.v:1509.5-1509.38" - process $proc$ls180.v:1509$3724 + process $proc$ls180.v:1509$3726 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always @@ -287540,7 +287566,7 @@ module \ls180 update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end attribute \src "ls180.v:1510.11-1510.51" - process $proc$ls180.v:1510$3725 + process $proc$ls180.v:1510$3727 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always @@ -287548,7 +287574,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end attribute \src "ls180.v:1552.11-1552.47" - process $proc$ls180.v:1552$3726 + process $proc$ls180.v:1552$3728 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always @@ -287556,7 +287582,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end attribute \src "ls180.v:1556.5-1556.49" - process $proc$ls180.v:1556$3727 + process $proc$ls180.v:1556$3729 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always @@ -287564,7 +287590,7 @@ module \ls180 update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end attribute \src "ls180.v:1560.5-1560.51" - process $proc$ls180.v:1560$3728 + process $proc$ls180.v:1560$3730 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always @@ -287572,7 +287598,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end attribute \src "ls180.v:1561.5-1561.51" - process $proc$ls180.v:1561$3729 + process $proc$ls180.v:1561$3731 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always @@ -287580,7 +287606,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end attribute \src "ls180.v:1562.5-1562.51" - process $proc$ls180.v:1562$3730 + process $proc$ls180.v:1562$3732 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always @@ -287588,7 +287614,7 @@ module \ls180 sync init end attribute \src "ls180.v:1563.5-1563.50" - process $proc$ls180.v:1563$3731 + process $proc$ls180.v:1563$3733 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always @@ -287596,7 +287622,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end attribute \src "ls180.v:1564.11-1564.64" - process $proc$ls180.v:1564$3732 + process $proc$ls180.v:1564$3734 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always @@ -287604,7 +287630,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end attribute \src "ls180.v:1565.11-1565.48" - process $proc$ls180.v:1565$3733 + process $proc$ls180.v:1565$3735 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always @@ -287612,7 +287638,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end attribute \src "ls180.v:1566.12-1566.59" - process $proc$ls180.v:1566$3734 + process $proc$ls180.v:1566$3736 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always @@ -287620,7 +287646,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end attribute \src "ls180.v:1570.12-1570.55" - process $proc$ls180.v:1570$3735 + process $proc$ls180.v:1570$3737 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always @@ -287628,7 +287654,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end attribute \src "ls180.v:1573.12-1573.59" - process $proc$ls180.v:1573$3736 + process $proc$ls180.v:1573$3738 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always @@ -287636,7 +287662,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end attribute \src "ls180.v:1577.12-1577.55" - process $proc$ls180.v:1577$3737 + process $proc$ls180.v:1577$3739 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always @@ -287644,7 +287670,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end attribute \src "ls180.v:1580.12-1580.59" - process $proc$ls180.v:1580$3738 + process $proc$ls180.v:1580$3740 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always @@ -287652,7 +287678,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end attribute \src "ls180.v:1584.12-1584.55" - process $proc$ls180.v:1584$3739 + process $proc$ls180.v:1584$3741 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always @@ -287660,7 +287686,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end attribute \src "ls180.v:1587.12-1587.59" - process $proc$ls180.v:1587$3740 + process $proc$ls180.v:1587$3742 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always @@ -287668,7 +287694,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end attribute \src "ls180.v:1591.12-1591.55" - process $proc$ls180.v:1591$3741 + process $proc$ls180.v:1591$3743 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always @@ -287676,7 +287702,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3742 + process $proc$ls180.v:1594$3744 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always @@ -287684,7 +287710,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end attribute \src "ls180.v:1595.12-1595.54" - process $proc$ls180.v:1595$3743 + process $proc$ls180.v:1595$3745 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always @@ -287692,7 +287718,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end attribute \src "ls180.v:1596.12-1596.54" - process $proc$ls180.v:1596$3744 + process $proc$ls180.v:1596$3746 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always @@ -287700,7 +287726,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end attribute \src "ls180.v:1597.12-1597.54" - process $proc$ls180.v:1597$3745 + process $proc$ls180.v:1597$3747 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always @@ -287708,7 +287734,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end attribute \src "ls180.v:1598.5-1598.48" - process $proc$ls180.v:1598$3746 + process $proc$ls180.v:1598$3748 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always @@ -287716,7 +287742,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end attribute \src "ls180.v:1599.5-1599.48" - process $proc$ls180.v:1599$3747 + process $proc$ls180.v:1599$3749 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always @@ -287724,7 +287750,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end attribute \src "ls180.v:1600.5-1600.48" - process $proc$ls180.v:1600$3748 + process $proc$ls180.v:1600$3750 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always @@ -287732,7 +287758,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end attribute \src "ls180.v:1601.5-1601.47" - process $proc$ls180.v:1601$3749 + process $proc$ls180.v:1601$3751 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always @@ -287740,7 +287766,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end attribute \src "ls180.v:1602.11-1602.61" - process $proc$ls180.v:1602$3750 + process $proc$ls180.v:1602$3752 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always @@ -287748,7 +287774,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end attribute \src "ls180.v:1603.5-1603.50" - process $proc$ls180.v:1603$3751 + process $proc$ls180.v:1603$3753 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always @@ -287756,7 +287782,7 @@ module \ls180 update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end attribute \src "ls180.v:1605.5-1605.50" - process $proc$ls180.v:1605$3752 + process $proc$ls180.v:1605$3754 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always @@ -287764,7 +287790,7 @@ module \ls180 sync init end attribute \src "ls180.v:1608.11-1608.47" - process $proc$ls180.v:1608$3753 + process $proc$ls180.v:1608$3755 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always @@ -287772,7 +287798,7 @@ module \ls180 update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end attribute \src "ls180.v:1609.11-1609.47" - process $proc$ls180.v:1609$3754 + process $proc$ls180.v:1609$3756 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always @@ -287780,7 +287806,7 @@ module \ls180 update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end attribute \src "ls180.v:1610.12-1610.58" - process $proc$ls180.v:1610$3755 + process $proc$ls180.v:1610$3757 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always @@ -287788,7 +287814,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end attribute \src "ls180.v:1614.12-1614.54" - process $proc$ls180.v:1614$3756 + process $proc$ls180.v:1614$3758 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always @@ -287796,7 +287822,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end attribute \src "ls180.v:1615.5-1615.46" - process $proc$ls180.v:1615$3757 + process $proc$ls180.v:1615$3759 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always @@ -287804,7 +287830,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end attribute \src "ls180.v:1617.12-1617.58" - process $proc$ls180.v:1617$3758 + process $proc$ls180.v:1617$3760 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always @@ -287812,7 +287838,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end attribute \src "ls180.v:1621.12-1621.54" - process $proc$ls180.v:1621$3759 + process $proc$ls180.v:1621$3761 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always @@ -287820,7 +287846,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end attribute \src "ls180.v:1622.5-1622.46" - process $proc$ls180.v:1622$3760 + process $proc$ls180.v:1622$3762 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always @@ -287828,7 +287854,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end attribute \src "ls180.v:1624.12-1624.58" - process $proc$ls180.v:1624$3761 + process $proc$ls180.v:1624$3763 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always @@ -287836,7 +287862,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end attribute \src "ls180.v:1628.12-1628.54" - process $proc$ls180.v:1628$3762 + process $proc$ls180.v:1628$3764 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always @@ -287844,7 +287870,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end attribute \src "ls180.v:1629.5-1629.46" - process $proc$ls180.v:1629$3763 + process $proc$ls180.v:1629$3765 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always @@ -287852,7 +287878,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end attribute \src "ls180.v:1631.12-1631.58" - process $proc$ls180.v:1631$3764 + process $proc$ls180.v:1631$3766 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always @@ -287860,7 +287886,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end attribute \src "ls180.v:1635.12-1635.54" - process $proc$ls180.v:1635$3765 + process $proc$ls180.v:1635$3767 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always @@ -287868,7 +287894,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end attribute \src "ls180.v:1636.5-1636.46" - process $proc$ls180.v:1636$3766 + process $proc$ls180.v:1636$3768 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always @@ -287876,7 +287902,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3767 + process $proc$ls180.v:1638$3769 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always @@ -287884,7 +287910,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end attribute \src "ls180.v:1639.12-1639.53" - process $proc$ls180.v:1639$3768 + process $proc$ls180.v:1639$3770 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always @@ -287892,7 +287918,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end attribute \src "ls180.v:1640.12-1640.53" - process $proc$ls180.v:1640$3769 + process $proc$ls180.v:1640$3771 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always @@ -287900,7 +287926,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end attribute \src "ls180.v:1641.12-1641.53" - process $proc$ls180.v:1641$3770 + process $proc$ls180.v:1641$3772 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always @@ -287908,7 +287934,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end attribute \src "ls180.v:1642.5-1642.43" - process $proc$ls180.v:1642$3771 + process $proc$ls180.v:1642$3773 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always @@ -287916,7 +287942,7 @@ module \ls180 update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3772 + process $proc$ls180.v:1643$3774 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always @@ -287924,7 +287950,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end attribute \src "ls180.v:1644.12-1644.51" - process $proc$ls180.v:1644$3773 + process $proc$ls180.v:1644$3775 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always @@ -287932,7 +287958,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end attribute \src "ls180.v:1645.12-1645.51" - process $proc$ls180.v:1645$3774 + process $proc$ls180.v:1645$3776 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always @@ -287940,7 +287966,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end attribute \src "ls180.v:1646.12-1646.51" - process $proc$ls180.v:1646$3775 + process $proc$ls180.v:1646$3777 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always @@ -287948,7 +287974,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end attribute \src "ls180.v:1648.11-1648.39" - process $proc$ls180.v:1648$3776 + process $proc$ls180.v:1648$3778 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always @@ -287956,7 +287982,7 @@ module \ls180 update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end attribute \src "ls180.v:1649.5-1649.32" - process $proc$ls180.v:1649$3777 + process $proc$ls180.v:1649$3779 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always @@ -287964,7 +287990,7 @@ module \ls180 update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end attribute \src "ls180.v:1650.5-1650.33" - process $proc$ls180.v:1650$3778 + process $proc$ls180.v:1650$3780 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always @@ -287972,7 +287998,7 @@ module \ls180 update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end attribute \src "ls180.v:1651.5-1651.35" - process $proc$ls180.v:1651$3779 + process $proc$ls180.v:1651$3781 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always @@ -287980,7 +288006,7 @@ module \ls180 update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end attribute \src "ls180.v:1653.12-1653.42" - process $proc$ls180.v:1653$3780 + process $proc$ls180.v:1653$3782 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always @@ -287988,7 +288014,7 @@ module \ls180 update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end attribute \src "ls180.v:1654.5-1654.33" - process $proc$ls180.v:1654$3781 + process $proc$ls180.v:1654$3783 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always @@ -287996,7 +288022,7 @@ module \ls180 update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end attribute \src "ls180.v:1655.5-1655.34" - process $proc$ls180.v:1655$3782 + process $proc$ls180.v:1655$3784 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always @@ -288004,7 +288030,7 @@ module \ls180 update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end attribute \src "ls180.v:1656.5-1656.36" - process $proc$ls180.v:1656$3783 + process $proc$ls180.v:1656$3785 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always @@ -288012,7 +288038,7 @@ module \ls180 update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end attribute \src "ls180.v:1665.11-1665.41" - process $proc$ls180.v:1665$3784 + process $proc$ls180.v:1665$3786 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always @@ -288020,7 +288046,7 @@ module \ls180 sync init end attribute \src "ls180.v:1666.11-1666.41" - process $proc$ls180.v:1666$3785 + process $proc$ls180.v:1666$3787 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always @@ -288028,7 +288054,7 @@ module \ls180 sync init end attribute \src "ls180.v:1689.11-1689.45" - process $proc$ls180.v:1689$3786 + process $proc$ls180.v:1689$3788 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always @@ -288036,7 +288062,7 @@ module \ls180 update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end attribute \src "ls180.v:1690.5-1690.41" - process $proc$ls180.v:1690$3787 + process $proc$ls180.v:1690$3789 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always @@ -288044,7 +288070,7 @@ module \ls180 sync init end attribute \src "ls180.v:1691.11-1691.47" - process $proc$ls180.v:1691$3788 + process $proc$ls180.v:1691$3790 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always @@ -288052,7 +288078,7 @@ module \ls180 update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end attribute \src "ls180.v:1692.11-1692.47" - process $proc$ls180.v:1692$3789 + process $proc$ls180.v:1692$3791 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always @@ -288060,15 +288086,23 @@ module \ls180 update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end attribute \src "ls180.v:1693.11-1693.50" - process $proc$ls180.v:1693$3790 + process $proc$ls180.v:1693$3792 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end + attribute \src "ls180.v:171.12-171.74" + process $proc$ls180.v:171$3152 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end attribute \src "ls180.v:1713.5-1713.51" - process $proc$ls180.v:1713$3791 + process $proc$ls180.v:1713$3793 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always @@ -288076,7 +288110,7 @@ module \ls180 update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end attribute \src "ls180.v:1714.5-1714.50" - process $proc$ls180.v:1714$3792 + process $proc$ls180.v:1714$3794 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always @@ -288084,7 +288118,7 @@ module \ls180 update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end attribute \src "ls180.v:1715.12-1715.66" - process $proc$ls180.v:1715$3793 + process $proc$ls180.v:1715$3795 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288092,7 +288126,7 @@ module \ls180 update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end attribute \src "ls180.v:1716.11-1716.77" - process $proc$ls180.v:1716$3794 + process $proc$ls180.v:1716$3796 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -288100,7 +288134,7 @@ module \ls180 update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1717.11-1717.50" - process $proc$ls180.v:1717$3795 + process $proc$ls180.v:1717$3797 assign { } { } assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always @@ -288108,7 +288142,7 @@ module \ls180 update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end attribute \src "ls180.v:1719.5-1719.49" - process $proc$ls180.v:1719$3796 + process $proc$ls180.v:1719$3798 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always @@ -288116,7 +288150,7 @@ module \ls180 update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end attribute \src "ls180.v:1725.5-1725.45" - process $proc$ls180.v:1725$3797 + process $proc$ls180.v:1725$3799 assign { } { } assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always @@ -288124,7 +288158,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end attribute \src "ls180.v:1727.12-1727.62" - process $proc$ls180.v:1727$3798 + process $proc$ls180.v:1727$3800 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always @@ -288132,7 +288166,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end attribute \src "ls180.v:1728.12-1728.60" - process $proc$ls180.v:1728$3799 + process $proc$ls180.v:1728$3801 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288140,7 +288174,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end attribute \src "ls180.v:1730.5-1730.57" - process $proc$ls180.v:1730$3800 + process $proc$ls180.v:1730$3802 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always @@ -288148,7 +288182,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end attribute \src "ls180.v:1734.12-1734.67" - process $proc$ls180.v:1734$3801 + process $proc$ls180.v:1734$3803 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288156,7 +288190,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end attribute \src "ls180.v:1735.5-1735.54" - process $proc$ls180.v:1735$3802 + process $proc$ls180.v:1735$3804 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always @@ -288164,7 +288198,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end attribute \src "ls180.v:1736.12-1736.69" - process $proc$ls180.v:1736$3803 + process $proc$ls180.v:1736$3805 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always @@ -288172,7 +288206,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end attribute \src "ls180.v:1737.5-1737.56" - process $proc$ls180.v:1737$3804 + process $proc$ls180.v:1737$3806 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always @@ -288180,7 +288214,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end attribute \src "ls180.v:1738.5-1738.61" - process $proc$ls180.v:1738$3805 + process $proc$ls180.v:1738$3807 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always @@ -288188,7 +288222,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end attribute \src "ls180.v:1739.5-1739.56" - process $proc$ls180.v:1739$3806 + process $proc$ls180.v:1739$3808 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always @@ -288196,7 +288230,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end attribute \src "ls180.v:1740.5-1740.53" - process $proc$ls180.v:1740$3807 + process $proc$ls180.v:1740$3809 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always @@ -288204,7 +288238,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end attribute \src "ls180.v:1742.5-1742.59" - process $proc$ls180.v:1742$3808 + process $proc$ls180.v:1742$3810 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always @@ -288212,7 +288246,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end attribute \src "ls180.v:1743.5-1743.54" - process $proc$ls180.v:1743$3809 + process $proc$ls180.v:1743$3811 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always @@ -288220,7 +288254,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end attribute \src "ls180.v:1745.12-1745.61" - process $proc$ls180.v:1745$3810 + process $proc$ls180.v:1745$3812 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always @@ -288228,7 +288262,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end attribute \src "ls180.v:1748.12-1748.43" - process $proc$ls180.v:1748$3811 + process $proc$ls180.v:1748$3813 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always @@ -288236,15 +288270,23 @@ module \ls180 update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end attribute \src "ls180.v:1749.12-1749.45" - process $proc$ls180.v:1749$3812 + process $proc$ls180.v:1749$3814 assign { } { } assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end + attribute \src "ls180.v:175.5-175.69" + process $proc$ls180.v:175$3153 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end attribute \src "ls180.v:1751.11-1751.41" - process $proc$ls180.v:1751$3813 + process $proc$ls180.v:1751$3815 assign { } { } assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always @@ -288252,7 +288294,7 @@ module \ls180 update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end attribute \src "ls180.v:1752.5-1752.35" - process $proc$ls180.v:1752$3814 + process $proc$ls180.v:1752$3816 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always @@ -288260,7 +288302,7 @@ module \ls180 update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end attribute \src "ls180.v:1753.5-1753.35" - process $proc$ls180.v:1753$3815 + process $proc$ls180.v:1753$3817 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always @@ -288268,7 +288310,7 @@ module \ls180 update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end attribute \src "ls180.v:1755.5-1755.34" - process $proc$ls180.v:1755$3816 + process $proc$ls180.v:1755$3818 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always @@ -288276,7 +288318,7 @@ module \ls180 update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end attribute \src "ls180.v:1756.11-1756.41" - process $proc$ls180.v:1756$3817 + process $proc$ls180.v:1756$3819 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always @@ -288284,23 +288326,15 @@ module \ls180 sync init end attribute \src "ls180.v:1757.11-1757.41" - process $proc$ls180.v:1757$3818 + process $proc$ls180.v:1757$3820 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:176.5-176.69" - process $proc$ls180.v:176$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end attribute \src "ls180.v:1764.5-1764.43" - process $proc$ls180.v:1764$3819 + process $proc$ls180.v:1764$3821 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always @@ -288308,7 +288342,7 @@ module \ls180 update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end attribute \src "ls180.v:1765.5-1765.43" - process $proc$ls180.v:1765$3820 + process $proc$ls180.v:1765$3822 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always @@ -288316,7 +288350,7 @@ module \ls180 update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end attribute \src "ls180.v:1766.5-1766.42" - process $proc$ls180.v:1766$3821 + process $proc$ls180.v:1766$3823 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always @@ -288324,7 +288358,7 @@ module \ls180 update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end attribute \src "ls180.v:1767.12-1767.61" - process $proc$ls180.v:1767$3822 + process $proc$ls180.v:1767$3824 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always @@ -288332,7 +288366,7 @@ module \ls180 update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end attribute \src "ls180.v:1768.5-1768.45" - process $proc$ls180.v:1768$3823 + process $proc$ls180.v:1768$3825 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always @@ -288340,7 +288374,7 @@ module \ls180 update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end attribute \src "ls180.v:1770.5-1770.45" - process $proc$ls180.v:1770$3824 + process $proc$ls180.v:1770$3826 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always @@ -288348,7 +288382,7 @@ module \ls180 sync init end attribute \src "ls180.v:1771.5-1771.44" - process $proc$ls180.v:1771$3825 + process $proc$ls180.v:1771$3827 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always @@ -288356,7 +288390,7 @@ module \ls180 update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end attribute \src "ls180.v:1772.12-1772.60" - process $proc$ls180.v:1772$3826 + process $proc$ls180.v:1772$3828 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288364,7 +288398,7 @@ module \ls180 update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end attribute \src "ls180.v:1773.12-1773.45" - process $proc$ls180.v:1773$3827 + process $proc$ls180.v:1773$3829 assign { } { } assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288372,7 +288406,7 @@ module \ls180 update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end attribute \src "ls180.v:1774.12-1774.53" - process $proc$ls180.v:1774$3828 + process $proc$ls180.v:1774$3830 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288380,7 +288414,7 @@ module \ls180 update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end attribute \src "ls180.v:1775.5-1775.40" - process $proc$ls180.v:1775$3829 + process $proc$ls180.v:1775$3831 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always @@ -288388,7 +288422,7 @@ module \ls180 update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end attribute \src "ls180.v:1776.12-1776.55" - process $proc$ls180.v:1776$3830 + process $proc$ls180.v:1776$3832 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always @@ -288396,7 +288430,7 @@ module \ls180 update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end attribute \src "ls180.v:1777.5-1777.42" - process $proc$ls180.v:1777$3831 + process $proc$ls180.v:1777$3833 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always @@ -288404,7 +288438,7 @@ module \ls180 update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end attribute \src "ls180.v:1778.5-1778.47" - process $proc$ls180.v:1778$3832 + process $proc$ls180.v:1778$3834 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always @@ -288412,7 +288446,7 @@ module \ls180 update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end attribute \src "ls180.v:1779.5-1779.42" - process $proc$ls180.v:1779$3833 + process $proc$ls180.v:1779$3835 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always @@ -288420,7 +288454,7 @@ module \ls180 update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end attribute \src "ls180.v:1780.5-1780.44" - process $proc$ls180.v:1780$3834 + process $proc$ls180.v:1780$3836 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always @@ -288428,7 +288462,7 @@ module \ls180 update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end attribute \src "ls180.v:1782.5-1782.45" - process $proc$ls180.v:1782$3835 + process $proc$ls180.v:1782$3837 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always @@ -288436,7 +288470,7 @@ module \ls180 update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end attribute \src "ls180.v:1783.5-1783.40" - process $proc$ls180.v:1783$3836 + process $proc$ls180.v:1783$3838 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always @@ -288444,7 +288478,7 @@ module \ls180 update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end attribute \src "ls180.v:1787.12-1787.47" - process $proc$ls180.v:1787$3837 + process $proc$ls180.v:1787$3839 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always @@ -288452,7 +288486,7 @@ module \ls180 update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end attribute \src "ls180.v:1799.11-1799.64" - process $proc$ls180.v:1799$3838 + process $proc$ls180.v:1799$3840 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always @@ -288460,23 +288494,15 @@ module \ls180 update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end attribute \src "ls180.v:1801.11-1801.48" - process $proc$ls180.v:1801$3839 + process $proc$ls180.v:1801$3841 assign { } { } assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:181.5-181.72" - process $proc$ls180.v:181$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end attribute \src "ls180.v:1825.11-1825.45" - process $proc$ls180.v:1825$3840 + process $proc$ls180.v:1825$3842 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always @@ -288484,7 +288510,7 @@ module \ls180 update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end attribute \src "ls180.v:1826.5-1826.41" - process $proc$ls180.v:1826$3841 + process $proc$ls180.v:1826$3843 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always @@ -288492,7 +288518,7 @@ module \ls180 sync init end attribute \src "ls180.v:1827.11-1827.47" - process $proc$ls180.v:1827$3842 + process $proc$ls180.v:1827$3844 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always @@ -288500,7 +288526,7 @@ module \ls180 update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end attribute \src "ls180.v:1828.11-1828.47" - process $proc$ls180.v:1828$3843 + process $proc$ls180.v:1828$3845 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always @@ -288508,23 +288534,15 @@ module \ls180 update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end attribute \src "ls180.v:1829.11-1829.50" - process $proc$ls180.v:1829$3844 + process $proc$ls180.v:1829$3846 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:184.11-184.79" - process $proc$ls180.v:184$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end attribute \src "ls180.v:1842.5-1842.36" - process $proc$ls180.v:1842$3845 + process $proc$ls180.v:1842$3847 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always @@ -288532,7 +288550,7 @@ module \ls180 update \builder_converter0_state $1\builder_converter0_state[0:0] end attribute \src "ls180.v:1843.5-1843.41" - process $proc$ls180.v:1843$3846 + process $proc$ls180.v:1843$3848 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always @@ -288540,7 +288558,7 @@ module \ls180 update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end attribute \src "ls180.v:1844.5-1844.57" - process $proc$ls180.v:1844$3847 + process $proc$ls180.v:1844$3849 assign { } { } assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always @@ -288548,7 +288566,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end attribute \src "ls180.v:1845.5-1845.60" - process $proc$ls180.v:1845$3848 + process $proc$ls180.v:1845$3850 assign { } { } assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always @@ -288556,7 +288574,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end attribute \src "ls180.v:1846.5-1846.36" - process $proc$ls180.v:1846$3849 + process $proc$ls180.v:1846$3851 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always @@ -288564,7 +288582,7 @@ module \ls180 update \builder_converter1_state $1\builder_converter1_state[0:0] end attribute \src "ls180.v:1847.5-1847.41" - process $proc$ls180.v:1847$3850 + process $proc$ls180.v:1847$3852 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always @@ -288572,7 +288590,7 @@ module \ls180 update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end attribute \src "ls180.v:1848.5-1848.57" - process $proc$ls180.v:1848$3851 + process $proc$ls180.v:1848$3853 assign { } { } assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always @@ -288580,7 +288598,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3852 + process $proc$ls180.v:1849$3854 assign { } { } assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always @@ -288588,7 +288606,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end attribute \src "ls180.v:1850.5-1850.36" - process $proc$ls180.v:1850$3853 + process $proc$ls180.v:1850$3855 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always @@ -288596,7 +288614,7 @@ module \ls180 update \builder_converter2_state $1\builder_converter2_state[0:0] end attribute \src "ls180.v:1851.5-1851.41" - process $proc$ls180.v:1851$3854 + process $proc$ls180.v:1851$3856 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always @@ -288604,7 +288622,7 @@ module \ls180 update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end attribute \src "ls180.v:1852.5-1852.60" - process $proc$ls180.v:1852$3855 + process $proc$ls180.v:1852$3857 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always @@ -288612,7 +288630,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end attribute \src "ls180.v:1853.5-1853.63" - process $proc$ls180.v:1853$3856 + process $proc$ls180.v:1853$3858 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always @@ -288620,7 +288638,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end attribute \src "ls180.v:1854.11-1854.41" - process $proc$ls180.v:1854$3857 + process $proc$ls180.v:1854$3859 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always @@ -288628,7 +288646,7 @@ module \ls180 update \builder_refresher_state $1\builder_refresher_state[1:0] end attribute \src "ls180.v:1855.11-1855.46" - process $proc$ls180.v:1855$3858 + process $proc$ls180.v:1855$3860 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always @@ -288636,7 +288654,7 @@ module \ls180 update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end attribute \src "ls180.v:1856.11-1856.44" - process $proc$ls180.v:1856$3859 + process $proc$ls180.v:1856$3861 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always @@ -288644,7 +288662,7 @@ module \ls180 update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end attribute \src "ls180.v:1857.11-1857.49" - process $proc$ls180.v:1857$3860 + process $proc$ls180.v:1857$3862 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always @@ -288652,7 +288670,7 @@ module \ls180 update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end attribute \src "ls180.v:1858.11-1858.44" - process $proc$ls180.v:1858$3861 + process $proc$ls180.v:1858$3863 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always @@ -288660,7 +288678,7 @@ module \ls180 update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end attribute \src "ls180.v:1859.11-1859.49" - process $proc$ls180.v:1859$3862 + process $proc$ls180.v:1859$3864 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always @@ -288668,7 +288686,7 @@ module \ls180 update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end attribute \src "ls180.v:1860.11-1860.44" - process $proc$ls180.v:1860$3863 + process $proc$ls180.v:1860$3865 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always @@ -288676,7 +288694,7 @@ module \ls180 update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end attribute \src "ls180.v:1861.11-1861.49" - process $proc$ls180.v:1861$3864 + process $proc$ls180.v:1861$3866 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always @@ -288684,7 +288702,7 @@ module \ls180 update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end attribute \src "ls180.v:1862.11-1862.44" - process $proc$ls180.v:1862$3865 + process $proc$ls180.v:1862$3867 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always @@ -288692,7 +288710,7 @@ module \ls180 update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end attribute \src "ls180.v:1863.11-1863.49" - process $proc$ls180.v:1863$3866 + process $proc$ls180.v:1863$3868 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always @@ -288700,7 +288718,7 @@ module \ls180 update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end attribute \src "ls180.v:1864.11-1864.43" - process $proc$ls180.v:1864$3867 + process $proc$ls180.v:1864$3869 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always @@ -288708,7 +288726,7 @@ module \ls180 update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end attribute \src "ls180.v:1865.11-1865.48" - process $proc$ls180.v:1865$3868 + process $proc$ls180.v:1865$3870 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always @@ -288716,7 +288734,7 @@ module \ls180 update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3869 + process $proc$ls180.v:1878$3871 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always @@ -288724,23 +288742,15 @@ module \ls180 sync init end attribute \src "ls180.v:1879.5-1879.27" - process $proc$ls180.v:1879$3870 + process $proc$ls180.v:1879$3872 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:188.12-188.78" - process $proc$ls180.v:188$3153 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end attribute \src "ls180.v:1880.5-1880.27" - process $proc$ls180.v:1880$3871 + process $proc$ls180.v:1880$3873 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always @@ -288748,7 +288758,7 @@ module \ls180 sync init end attribute \src "ls180.v:1881.5-1881.27" - process $proc$ls180.v:1881$3872 + process $proc$ls180.v:1881$3874 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always @@ -288756,7 +288766,7 @@ module \ls180 sync init end attribute \src "ls180.v:1882.5-1882.42" - process $proc$ls180.v:1882$3873 + process $proc$ls180.v:1882$3875 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always @@ -288764,7 +288774,7 @@ module \ls180 update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3874 + process $proc$ls180.v:1883$3876 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always @@ -288772,7 +288782,7 @@ module \ls180 update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end attribute \src "ls180.v:1884.5-1884.43" - process $proc$ls180.v:1884$3875 + process $proc$ls180.v:1884$3877 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always @@ -288780,7 +288790,7 @@ module \ls180 update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end attribute \src "ls180.v:1885.5-1885.43" - process $proc$ls180.v:1885$3876 + process $proc$ls180.v:1885$3878 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always @@ -288788,7 +288798,7 @@ module \ls180 update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end attribute \src "ls180.v:1886.5-1886.43" - process $proc$ls180.v:1886$3877 + process $proc$ls180.v:1886$3879 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always @@ -288796,7 +288806,7 @@ module \ls180 update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end attribute \src "ls180.v:1887.5-1887.35" - process $proc$ls180.v:1887$3878 + process $proc$ls180.v:1887$3880 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always @@ -288804,7 +288814,7 @@ module \ls180 update \builder_converter_state $1\builder_converter_state[0:0] end attribute \src "ls180.v:1888.5-1888.40" - process $proc$ls180.v:1888$3879 + process $proc$ls180.v:1888$3881 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always @@ -288812,15 +288822,23 @@ module \ls180 update \builder_converter_next_state $1\builder_converter_next_state[0:0] end attribute \src "ls180.v:1889.5-1889.55" - process $proc$ls180.v:1889$3880 + process $proc$ls180.v:1889$3882 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end + attribute \src "ls180.v:189.12-189.78" + process $proc$ls180.v:189$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end attribute \src "ls180.v:1890.5-1890.58" - process $proc$ls180.v:1890$3881 + process $proc$ls180.v:1890$3883 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always @@ -288828,7 +288846,7 @@ module \ls180 update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end attribute \src "ls180.v:1891.11-1891.42" - process $proc$ls180.v:1891$3882 + process $proc$ls180.v:1891$3884 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always @@ -288836,7 +288854,7 @@ module \ls180 update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end attribute \src "ls180.v:1892.11-1892.47" - process $proc$ls180.v:1892$3883 + process $proc$ls180.v:1892$3885 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always @@ -288844,7 +288862,7 @@ module \ls180 update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end attribute \src "ls180.v:1893.11-1893.62" - process $proc$ls180.v:1893$3884 + process $proc$ls180.v:1893$3886 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always @@ -288852,7 +288870,7 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end attribute \src "ls180.v:1894.5-1894.59" - process $proc$ls180.v:1894$3885 + process $proc$ls180.v:1894$3887 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always @@ -288860,7 +288878,7 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end attribute \src "ls180.v:1895.11-1895.42" - process $proc$ls180.v:1895$3886 + process $proc$ls180.v:1895$3888 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always @@ -288868,7 +288886,7 @@ module \ls180 update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end attribute \src "ls180.v:1896.11-1896.47" - process $proc$ls180.v:1896$3887 + process $proc$ls180.v:1896$3889 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always @@ -288876,7 +288894,7 @@ module \ls180 update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end attribute \src "ls180.v:1897.11-1897.60" - process $proc$ls180.v:1897$3888 + process $proc$ls180.v:1897$3890 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always @@ -288884,7 +288902,7 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end attribute \src "ls180.v:1898.5-1898.57" - process $proc$ls180.v:1898$3889 + process $proc$ls180.v:1898$3891 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always @@ -288892,7 +288910,7 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end attribute \src "ls180.v:1899.5-1899.41" - process $proc$ls180.v:1899$3890 + process $proc$ls180.v:1899$3892 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always @@ -288900,7 +288918,7 @@ module \ls180 update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end attribute \src "ls180.v:1900.5-1900.46" - process $proc$ls180.v:1900$3891 + process $proc$ls180.v:1900$3893 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always @@ -288908,7 +288926,7 @@ module \ls180 update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end attribute \src "ls180.v:1901.11-1901.66" - process $proc$ls180.v:1901$3892 + process $proc$ls180.v:1901$3894 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always @@ -288916,7 +288934,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end attribute \src "ls180.v:1902.5-1902.63" - process $proc$ls180.v:1902$3893 + process $proc$ls180.v:1902$3895 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always @@ -288924,7 +288942,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end attribute \src "ls180.v:1903.11-1903.47" - process $proc$ls180.v:1903$3894 + process $proc$ls180.v:1903$3896 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always @@ -288932,7 +288950,7 @@ module \ls180 update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end attribute \src "ls180.v:1904.11-1904.52" - process $proc$ls180.v:1904$3895 + process $proc$ls180.v:1904$3897 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always @@ -288940,7 +288958,7 @@ module \ls180 update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end attribute \src "ls180.v:1905.11-1905.66" - process $proc$ls180.v:1905$3896 + process $proc$ls180.v:1905$3898 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always @@ -288948,7 +288966,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end attribute \src "ls180.v:1906.5-1906.63" - process $proc$ls180.v:1906$3897 + process $proc$ls180.v:1906$3899 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always @@ -288956,7 +288974,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end attribute \src "ls180.v:1907.11-1907.47" - process $proc$ls180.v:1907$3898 + process $proc$ls180.v:1907$3900 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always @@ -288964,7 +288982,7 @@ module \ls180 update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end attribute \src "ls180.v:1908.11-1908.52" - process $proc$ls180.v:1908$3899 + process $proc$ls180.v:1908$3901 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always @@ -288972,7 +288990,7 @@ module \ls180 update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end attribute \src "ls180.v:1909.11-1909.67" - process $proc$ls180.v:1909$3900 + process $proc$ls180.v:1909$3902 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always @@ -288980,7 +288998,7 @@ module \ls180 update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end attribute \src "ls180.v:1910.5-1910.64" - process $proc$ls180.v:1910$3901 + process $proc$ls180.v:1910$3903 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always @@ -288988,7 +289006,7 @@ module \ls180 update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end attribute \src "ls180.v:1911.12-1911.71" - process $proc$ls180.v:1911$3902 + process $proc$ls180.v:1911$3904 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always @@ -288996,7 +289014,7 @@ module \ls180 update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end attribute \src "ls180.v:1912.5-1912.66" - process $proc$ls180.v:1912$3903 + process $proc$ls180.v:1912$3905 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always @@ -289004,7 +289022,7 @@ module \ls180 update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end attribute \src "ls180.v:1913.5-1913.66" - process $proc$ls180.v:1913$3904 + process $proc$ls180.v:1913$3906 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always @@ -289012,7 +289030,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end attribute \src "ls180.v:1914.5-1914.69" - process $proc$ls180.v:1914$3905 + process $proc$ls180.v:1914$3907 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always @@ -289020,7 +289038,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end attribute \src "ls180.v:1915.5-1915.41" - process $proc$ls180.v:1915$3906 + process $proc$ls180.v:1915$3908 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always @@ -289028,7 +289046,7 @@ module \ls180 update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end attribute \src "ls180.v:1916.5-1916.46" - process $proc$ls180.v:1916$3907 + process $proc$ls180.v:1916$3909 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always @@ -289036,7 +289054,7 @@ module \ls180 update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end attribute \src "ls180.v:1917.5-1917.66" - process $proc$ls180.v:1917$3908 + process $proc$ls180.v:1917$3910 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always @@ -289044,7 +289062,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end attribute \src "ls180.v:1918.5-1918.69" - process $proc$ls180.v:1918$3909 + process $proc$ls180.v:1918$3911 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always @@ -289052,7 +289070,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end attribute \src "ls180.v:1919.11-1919.41" - process $proc$ls180.v:1919$3910 + process $proc$ls180.v:1919$3912 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always @@ -289060,7 +289078,7 @@ module \ls180 update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end attribute \src "ls180.v:1920.11-1920.46" - process $proc$ls180.v:1920$3911 + process $proc$ls180.v:1920$3913 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always @@ -289068,7 +289086,7 @@ module \ls180 update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end attribute \src "ls180.v:1921.11-1921.61" - process $proc$ls180.v:1921$3912 + process $proc$ls180.v:1921$3914 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always @@ -289076,7 +289094,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end attribute \src "ls180.v:1922.5-1922.58" - process $proc$ls180.v:1922$3913 + process $proc$ls180.v:1922$3915 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always @@ -289084,7 +289102,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end attribute \src "ls180.v:1923.11-1923.48" - process $proc$ls180.v:1923$3914 + process $proc$ls180.v:1923$3916 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always @@ -289092,7 +289110,7 @@ module \ls180 update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end attribute \src "ls180.v:1924.11-1924.53" - process $proc$ls180.v:1924$3915 + process $proc$ls180.v:1924$3917 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always @@ -289100,7 +289118,7 @@ module \ls180 update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end attribute \src "ls180.v:1925.11-1925.70" - process $proc$ls180.v:1925$3916 + process $proc$ls180.v:1925$3918 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always @@ -289108,7 +289126,7 @@ module \ls180 update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end attribute \src "ls180.v:1926.5-1926.66" - process $proc$ls180.v:1926$3917 + process $proc$ls180.v:1926$3919 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always @@ -289116,7 +289134,7 @@ module \ls180 update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end attribute \src "ls180.v:1927.12-1927.73" - process $proc$ls180.v:1927$3918 + process $proc$ls180.v:1927$3920 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always @@ -289124,7 +289142,7 @@ module \ls180 update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end attribute \src "ls180.v:1928.5-1928.68" - process $proc$ls180.v:1928$3919 + process $proc$ls180.v:1928$3921 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always @@ -289132,7 +289150,7 @@ module \ls180 update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end attribute \src "ls180.v:1929.5-1929.69" - process $proc$ls180.v:1929$3920 + process $proc$ls180.v:1929$3922 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always @@ -289140,7 +289158,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end attribute \src "ls180.v:1930.5-1930.72" - process $proc$ls180.v:1930$3921 + process $proc$ls180.v:1930$3923 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always @@ -289148,7 +289166,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end attribute \src "ls180.v:1931.5-1931.52" - process $proc$ls180.v:1931$3922 + process $proc$ls180.v:1931$3924 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always @@ -289156,7 +289174,7 @@ module \ls180 update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end attribute \src "ls180.v:1932.5-1932.57" - process $proc$ls180.v:1932$3923 + process $proc$ls180.v:1932$3925 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always @@ -289164,7 +289182,7 @@ module \ls180 update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end attribute \src "ls180.v:1933.12-1933.93" - process $proc$ls180.v:1933$3924 + process $proc$ls180.v:1933$3926 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always @@ -289172,7 +289190,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end attribute \src "ls180.v:1934.5-1934.88" - process $proc$ls180.v:1934$3925 + process $proc$ls180.v:1934$3927 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always @@ -289180,7 +289198,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end attribute \src "ls180.v:1935.12-1935.93" - process $proc$ls180.v:1935$3926 + process $proc$ls180.v:1935$3928 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always @@ -289188,7 +289206,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end attribute \src "ls180.v:1936.5-1936.88" - process $proc$ls180.v:1936$3927 + process $proc$ls180.v:1936$3929 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always @@ -289196,7 +289214,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end attribute \src "ls180.v:1937.12-1937.93" - process $proc$ls180.v:1937$3928 + process $proc$ls180.v:1937$3930 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always @@ -289204,7 +289222,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end attribute \src "ls180.v:1938.5-1938.88" - process $proc$ls180.v:1938$3929 + process $proc$ls180.v:1938$3931 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always @@ -289212,7 +289230,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end attribute \src "ls180.v:1939.12-1939.93" - process $proc$ls180.v:1939$3930 + process $proc$ls180.v:1939$3932 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always @@ -289220,7 +289238,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end attribute \src "ls180.v:1940.5-1940.88" - process $proc$ls180.v:1940$3931 + process $proc$ls180.v:1940$3933 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always @@ -289228,7 +289246,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end attribute \src "ls180.v:1941.11-1941.87" - process $proc$ls180.v:1941$3932 + process $proc$ls180.v:1941$3934 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always @@ -289236,7 +289254,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end attribute \src "ls180.v:1942.5-1942.84" - process $proc$ls180.v:1942$3933 + process $proc$ls180.v:1942$3935 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always @@ -289244,7 +289262,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end attribute \src "ls180.v:1943.11-1943.42" - process $proc$ls180.v:1943$3934 + process $proc$ls180.v:1943$3936 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always @@ -289252,7 +289270,7 @@ module \ls180 update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end attribute \src "ls180.v:1944.11-1944.47" - process $proc$ls180.v:1944$3935 + process $proc$ls180.v:1944$3937 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always @@ -289260,7 +289278,7 @@ module \ls180 update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end attribute \src "ls180.v:1945.5-1945.55" - process $proc$ls180.v:1945$3936 + process $proc$ls180.v:1945$3938 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always @@ -289268,7 +289286,7 @@ module \ls180 update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end attribute \src "ls180.v:1946.5-1946.58" - process $proc$ls180.v:1946$3937 + process $proc$ls180.v:1946$3939 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always @@ -289276,7 +289294,7 @@ module \ls180 update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end attribute \src "ls180.v:1947.5-1947.56" - process $proc$ls180.v:1947$3938 + process $proc$ls180.v:1947$3940 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always @@ -289284,7 +289302,7 @@ module \ls180 update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end attribute \src "ls180.v:1948.5-1948.59" - process $proc$ls180.v:1948$3939 + process $proc$ls180.v:1948$3941 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always @@ -289292,7 +289310,7 @@ module \ls180 update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end attribute \src "ls180.v:1949.11-1949.62" - process $proc$ls180.v:1949$3940 + process $proc$ls180.v:1949$3942 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always @@ -289300,7 +289318,7 @@ module \ls180 update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end attribute \src "ls180.v:1950.5-1950.59" - process $proc$ls180.v:1950$3941 + process $proc$ls180.v:1950$3943 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always @@ -289308,7 +289326,7 @@ module \ls180 update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end attribute \src "ls180.v:1951.12-1951.65" - process $proc$ls180.v:1951$3942 + process $proc$ls180.v:1951$3944 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always @@ -289316,7 +289334,7 @@ module \ls180 update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end attribute \src "ls180.v:1952.5-1952.60" - process $proc$ls180.v:1952$3943 + process $proc$ls180.v:1952$3945 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always @@ -289324,7 +289342,7 @@ module \ls180 update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end attribute \src "ls180.v:1953.5-1953.56" - process $proc$ls180.v:1953$3944 + process $proc$ls180.v:1953$3946 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always @@ -289332,7 +289350,7 @@ module \ls180 update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end attribute \src "ls180.v:1954.5-1954.59" - process $proc$ls180.v:1954$3945 + process $proc$ls180.v:1954$3947 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always @@ -289340,7 +289358,7 @@ module \ls180 update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end attribute \src "ls180.v:1955.5-1955.58" - process $proc$ls180.v:1955$3946 + process $proc$ls180.v:1955$3948 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always @@ -289348,7 +289366,7 @@ module \ls180 update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end attribute \src "ls180.v:1956.5-1956.61" - process $proc$ls180.v:1956$3947 + process $proc$ls180.v:1956$3949 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always @@ -289356,7 +289374,7 @@ module \ls180 update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end attribute \src "ls180.v:1957.5-1957.57" - process $proc$ls180.v:1957$3948 + process $proc$ls180.v:1957$3950 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always @@ -289364,7 +289382,7 @@ module \ls180 update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end attribute \src "ls180.v:1958.5-1958.60" - process $proc$ls180.v:1958$3949 + process $proc$ls180.v:1958$3951 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always @@ -289372,7 +289390,7 @@ module \ls180 update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end attribute \src "ls180.v:1959.5-1959.59" - process $proc$ls180.v:1959$3950 + process $proc$ls180.v:1959$3952 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always @@ -289380,7 +289398,7 @@ module \ls180 update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end attribute \src "ls180.v:1960.5-1960.62" - process $proc$ls180.v:1960$3951 + process $proc$ls180.v:1960$3953 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always @@ -289388,7 +289406,7 @@ module \ls180 update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end attribute \src "ls180.v:1961.13-1961.76" - process $proc$ls180.v:1961$3952 + process $proc$ls180.v:1961$3954 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289396,7 +289414,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end attribute \src "ls180.v:1962.5-1962.69" - process $proc$ls180.v:1962$3953 + process $proc$ls180.v:1962$3955 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always @@ -289404,7 +289422,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end attribute \src "ls180.v:1963.11-1963.46" - process $proc$ls180.v:1963$3954 + process $proc$ls180.v:1963$3956 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always @@ -289412,7 +289430,7 @@ module \ls180 update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end attribute \src "ls180.v:1964.11-1964.51" - process $proc$ls180.v:1964$3955 + process $proc$ls180.v:1964$3957 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always @@ -289420,7 +289438,7 @@ module \ls180 update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end attribute \src "ls180.v:1965.12-1965.87" - process $proc$ls180.v:1965$3956 + process $proc$ls180.v:1965$3958 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always @@ -289428,7 +289446,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end attribute \src "ls180.v:1966.5-1966.82" - process $proc$ls180.v:1966$3957 + process $proc$ls180.v:1966$3959 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always @@ -289436,7 +289454,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end attribute \src "ls180.v:1967.5-1967.44" - process $proc$ls180.v:1967$3958 + process $proc$ls180.v:1967$3960 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always @@ -289444,7 +289462,7 @@ module \ls180 update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end attribute \src "ls180.v:1968.5-1968.49" - process $proc$ls180.v:1968$3959 + process $proc$ls180.v:1968$3961 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always @@ -289452,7 +289470,7 @@ module \ls180 update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end attribute \src "ls180.v:1969.12-1969.75" - process $proc$ls180.v:1969$3960 + process $proc$ls180.v:1969$3962 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289460,7 +289478,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end attribute \src "ls180.v:1970.5-1970.70" - process $proc$ls180.v:1970$3961 + process $proc$ls180.v:1970$3963 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always @@ -289468,7 +289486,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end attribute \src "ls180.v:1971.11-1971.60" - process $proc$ls180.v:1971$3962 + process $proc$ls180.v:1971$3964 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always @@ -289476,7 +289494,7 @@ module \ls180 update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end attribute \src "ls180.v:1972.11-1972.65" - process $proc$ls180.v:1972$3963 + process $proc$ls180.v:1972$3965 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always @@ -289484,7 +289502,7 @@ module \ls180 update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end attribute \src "ls180.v:1973.12-1973.87" - process $proc$ls180.v:1973$3964 + process $proc$ls180.v:1973$3966 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always @@ -289492,7 +289510,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end attribute \src "ls180.v:1974.5-1974.82" - process $proc$ls180.v:1974$3965 + process $proc$ls180.v:1974$3967 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always @@ -289500,7 +289518,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end attribute \src "ls180.v:1975.12-1975.43" - process $proc$ls180.v:1975$3966 + process $proc$ls180.v:1975$3968 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always @@ -289508,7 +289526,7 @@ module \ls180 update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end attribute \src "ls180.v:1976.5-1976.34" - process $proc$ls180.v:1976$3967 + process $proc$ls180.v:1976$3969 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always @@ -289516,7 +289534,7 @@ module \ls180 update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end attribute \src "ls180.v:1977.11-1977.43" - process $proc$ls180.v:1977$3968 + process $proc$ls180.v:1977$3970 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always @@ -289524,7 +289542,7 @@ module \ls180 update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end attribute \src "ls180.v:1979.12-1979.52" - process $proc$ls180.v:1979$3969 + process $proc$ls180.v:1979$3971 assign { } { } assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always @@ -289532,7 +289550,7 @@ module \ls180 sync init end attribute \src "ls180.v:1980.12-1980.54" - process $proc$ls180.v:1980$3970 + process $proc$ls180.v:1980$3972 assign { } { } assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always @@ -289540,7 +289558,7 @@ module \ls180 sync init end attribute \src "ls180.v:1981.12-1981.54" - process $proc$ls180.v:1981$3971 + process $proc$ls180.v:1981$3973 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always @@ -289548,7 +289566,7 @@ module \ls180 update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end attribute \src "ls180.v:1982.11-1982.50" - process $proc$ls180.v:1982$3972 + process $proc$ls180.v:1982$3974 assign { } { } assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always @@ -289556,7 +289574,7 @@ module \ls180 sync init end attribute \src "ls180.v:1983.5-1983.44" - process $proc$ls180.v:1983$3973 + process $proc$ls180.v:1983$3975 assign { } { } assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always @@ -289564,7 +289582,7 @@ module \ls180 sync init end attribute \src "ls180.v:1984.5-1984.44" - process $proc$ls180.v:1984$3974 + process $proc$ls180.v:1984$3976 assign { } { } assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always @@ -289572,7 +289590,7 @@ module \ls180 sync init end attribute \src "ls180.v:1985.5-1985.44" - process $proc$ls180.v:1985$3975 + process $proc$ls180.v:1985$3977 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always @@ -289580,7 +289598,7 @@ module \ls180 update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end attribute \src "ls180.v:1986.5-1986.43" - process $proc$ls180.v:1986$3976 + process $proc$ls180.v:1986$3978 assign { } { } assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always @@ -289588,7 +289606,7 @@ module \ls180 sync init end attribute \src "ls180.v:1989.12-1989.65" - process $proc$ls180.v:1989$3977 + process $proc$ls180.v:1989$3979 assign { } { } assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289596,7 +289614,7 @@ module \ls180 sync init end attribute \src "ls180.v:1993.5-1993.55" - process $proc$ls180.v:1993$3978 + process $proc$ls180.v:1993$3980 assign { } { } assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always @@ -289604,7 +289622,7 @@ module \ls180 sync init end attribute \src "ls180.v:1997.5-1997.55" - process $proc$ls180.v:1997$3979 + process $proc$ls180.v:1997$3981 assign { } { } assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always @@ -289612,7 +289630,7 @@ module \ls180 sync init end attribute \src "ls180.v:2000.12-2000.40" - process $proc$ls180.v:2000$3980 + process $proc$ls180.v:2000$3982 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always @@ -289620,15 +289638,23 @@ module \ls180 update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end attribute \src "ls180.v:2004.5-2004.30" - process $proc$ls180.v:2004$3981 + process $proc$ls180.v:2004$3983 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always sync init update \builder_shared_ack $1\builder_shared_ack[0:0] end + attribute \src "ls180.v:201.5-201.72" + process $proc$ls180.v:201$3155 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end attribute \src "ls180.v:2010.11-2010.31" - process $proc$ls180.v:2010$3982 + process $proc$ls180.v:2010$3984 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always @@ -289636,7 +289662,7 @@ module \ls180 update \builder_grant $1\builder_grant[2:0] end attribute \src "ls180.v:2011.12-2011.37" - process $proc$ls180.v:2011$3983 + process $proc$ls180.v:2011$3985 assign { } { } assign $1\builder_slave_sel[12:0] 13'0000000000000 sync always @@ -289644,7 +289670,7 @@ module \ls180 update \builder_slave_sel $1\builder_slave_sel[12:0] end attribute \src "ls180.v:2012.12-2012.39" - process $proc$ls180.v:2012$3984 + process $proc$ls180.v:2012$3986 assign { } { } assign $1\builder_slave_sel_r[12:0] 13'0000000000000 sync always @@ -289652,7 +289678,7 @@ module \ls180 update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] end attribute \src "ls180.v:2013.5-2013.25" - process $proc$ls180.v:2013$3985 + process $proc$ls180.v:2013$3987 assign { } { } assign $1\builder_error[0:0] 1'0 sync always @@ -289660,7 +289686,7 @@ module \ls180 update \builder_error $1\builder_error[0:0] end attribute \src "ls180.v:2016.12-2016.39" - process $proc$ls180.v:2016$3986 + process $proc$ls180.v:2016$3988 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always @@ -289668,23 +289694,23 @@ module \ls180 update \builder_count $1\builder_count[19:0] end attribute \src "ls180.v:2020.11-2020.51" - process $proc$ls180.v:2020$3987 + process $proc$ls180.v:2020$3989 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:204.12-204.74" - process $proc$ls180.v:204$3154 + attribute \src "ls180.v:204.11-204.79" + process $proc$ls180.v:204$3156 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] sync init end attribute \src "ls180.v:2061.11-2061.51" - process $proc$ls180.v:2061$3988 + process $proc$ls180.v:2061$3990 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289692,7 +289718,7 @@ module \ls180 update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2090.11-2090.51" - process $proc$ls180.v:2090$3989 + process $proc$ls180.v:2090$3991 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289700,7 +289726,7 @@ module \ls180 update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2103.11-2103.51" - process $proc$ls180.v:2103$3990 + process $proc$ls180.v:2103$3992 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289708,7 +289734,7 @@ module \ls180 update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$3155 + process $proc$ls180.v:213$3157 assign { } { } assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always @@ -289716,7 +289742,7 @@ module \ls180 update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end attribute \src "ls180.v:2144.11-2144.51" - process $proc$ls180.v:2144$3991 + process $proc$ls180.v:2144$3993 assign { } { } assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289724,7 +289750,7 @@ module \ls180 update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end attribute \src "ls180.v:217.5-217.40" - process $proc$ls180.v:217$3156 + process $proc$ls180.v:217$3158 assign { } { } assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always @@ -289732,7 +289758,7 @@ module \ls180 sync init end attribute \src "ls180.v:2185.11-2185.51" - process $proc$ls180.v:2185$3992 + process $proc$ls180.v:2185$3994 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289740,7 +289766,7 @@ module \ls180 update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end attribute \src "ls180.v:220.11-220.37" - process $proc$ls180.v:220$3157 + process $proc$ls180.v:220$3159 assign { } { } assign $1\main_libresocsim_we[7:0] 8'00000000 sync always @@ -289748,7 +289774,7 @@ module \ls180 update \main_libresocsim_we $1\main_libresocsim_we[7:0] end attribute \src "ls180.v:222.12-222.49" - process $proc$ls180.v:222$3158 + process $proc$ls180.v:222$3160 assign { } { } assign $1\main_libresocsim_load_storage[31:0] 0 sync always @@ -289756,7 +289782,7 @@ module \ls180 update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end attribute \src "ls180.v:223.5-223.36" - process $proc$ls180.v:223$3159 + process $proc$ls180.v:223$3161 assign { } { } assign $1\main_libresocsim_load_re[0:0] 1'0 sync always @@ -289764,7 +289790,7 @@ module \ls180 update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end attribute \src "ls180.v:224.12-224.51" - process $proc$ls180.v:224$3160 + process $proc$ls180.v:224$3162 assign { } { } assign $1\main_libresocsim_reload_storage[31:0] 0 sync always @@ -289772,7 +289798,7 @@ module \ls180 update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end attribute \src "ls180.v:225.5-225.38" - process $proc$ls180.v:225$3161 + process $proc$ls180.v:225$3163 assign { } { } assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always @@ -289780,7 +289806,7 @@ module \ls180 update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end attribute \src "ls180.v:2250.11-2250.51" - process $proc$ls180.v:2250$3993 + process $proc$ls180.v:2250$3995 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289788,7 +289814,7 @@ module \ls180 update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end attribute \src "ls180.v:226.5-226.39" - process $proc$ls180.v:226$3162 + process $proc$ls180.v:226$3164 assign { } { } assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always @@ -289796,7 +289822,7 @@ module \ls180 update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end attribute \src "ls180.v:227.5-227.34" - process $proc$ls180.v:227$3163 + process $proc$ls180.v:227$3165 assign { } { } assign $1\main_libresocsim_en_re[0:0] 1'0 sync always @@ -289804,7 +289830,7 @@ module \ls180 update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end attribute \src "ls180.v:228.5-228.49" - process $proc$ls180.v:228$3164 + process $proc$ls180.v:228$3166 assign { } { } assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always @@ -289812,7 +289838,7 @@ module \ls180 update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end attribute \src "ls180.v:229.5-229.44" - process $proc$ls180.v:229$3165 + process $proc$ls180.v:229$3167 assign { } { } assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always @@ -289820,7 +289846,7 @@ module \ls180 update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end attribute \src "ls180.v:230.12-230.49" - process $proc$ls180.v:230$3166 + process $proc$ls180.v:230$3168 assign { } { } assign $1\main_libresocsim_value_status[31:0] 0 sync always @@ -289828,7 +289854,7 @@ module \ls180 update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end attribute \src "ls180.v:234.5-234.41" - process $proc$ls180.v:234$3167 + process $proc$ls180.v:234$3169 assign { } { } assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always @@ -289836,7 +289862,7 @@ module \ls180 update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end attribute \src "ls180.v:236.5-236.39" - process $proc$ls180.v:236$3168 + process $proc$ls180.v:236$3170 assign { } { } assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always @@ -289844,7 +289870,7 @@ module \ls180 update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end attribute \src "ls180.v:237.5-237.45" - process $proc$ls180.v:237$3169 + process $proc$ls180.v:237$3171 assign { } { } assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always @@ -289852,7 +289878,7 @@ module \ls180 update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end attribute \src "ls180.v:2383.11-2383.51" - process $proc$ls180.v:2383$3994 + process $proc$ls180.v:2383$3996 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289860,7 +289886,7 @@ module \ls180 update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end attribute \src "ls180.v:246.5-246.49" - process $proc$ls180.v:246$3170 + process $proc$ls180.v:246$3172 assign { } { } assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always @@ -289868,7 +289894,7 @@ module \ls180 update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end attribute \src "ls180.v:2464.11-2464.51" - process $proc$ls180.v:2464$3995 + process $proc$ls180.v:2464$3997 assign { } { } assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289876,7 +289902,7 @@ module \ls180 update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end attribute \src "ls180.v:247.5-247.44" - process $proc$ls180.v:247$3171 + process $proc$ls180.v:247$3173 assign { } { } assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always @@ -289884,7 +289910,7 @@ module \ls180 update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end attribute \src "ls180.v:248.12-248.42" - process $proc$ls180.v:248$3172 + process $proc$ls180.v:248$3174 assign { } { } assign $1\main_libresocsim_value[31:0] 0 sync always @@ -289892,7 +289918,7 @@ module \ls180 update \main_libresocsim_value $1\main_libresocsim_value[31:0] end attribute \src "ls180.v:2481.11-2481.51" - process $proc$ls180.v:2481$3996 + process $proc$ls180.v:2481$3998 assign { } { } assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289900,7 +289926,7 @@ module \ls180 update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2522.11-2522.52" - process $proc$ls180.v:2522$3997 + process $proc$ls180.v:2522$3999 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289908,7 +289934,7 @@ module \ls180 update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$3173 + process $proc$ls180.v:255$3175 assign { } { } assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always @@ -289916,7 +289942,7 @@ module \ls180 update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end attribute \src "ls180.v:2555.11-2555.52" - process $proc$ls180.v:2555$3998 + process $proc$ls180.v:2555$4000 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289924,7 +289950,7 @@ module \ls180 update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end attribute \src "ls180.v:259.5-259.39" - process $proc$ls180.v:259$3174 + process $proc$ls180.v:259$3176 assign { } { } assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always @@ -289932,7 +289958,7 @@ module \ls180 sync init end attribute \src "ls180.v:2596.11-2596.52" - process $proc$ls180.v:2596$3999 + process $proc$ls180.v:2596$4001 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289940,7 +289966,7 @@ module \ls180 update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end attribute \src "ls180.v:262.11-262.31" - process $proc$ls180.v:262$3175 + process $proc$ls180.v:262$3177 assign { } { } assign $1\main_sram0_we[7:0] 8'00000000 sync always @@ -289948,7 +289974,7 @@ module \ls180 update \main_sram0_we $1\main_sram0_we[7:0] end attribute \src "ls180.v:2661.11-2661.52" - process $proc$ls180.v:2661$4000 + process $proc$ls180.v:2661$4002 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289956,7 +289982,7 @@ module \ls180 update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2686.11-2686.52" - process $proc$ls180.v:2686$4001 + process $proc$ls180.v:2686$4003 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289964,7 +289990,7 @@ module \ls180 update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$3176 + process $proc$ls180.v:270$3178 assign { } { } assign $1\main_interface1_ram_bus_ack[0:0] 1'0 sync always @@ -289972,7 +289998,7 @@ module \ls180 update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] end attribute \src "ls180.v:2708.11-2708.31" - process $proc$ls180.v:2708$4002 + process $proc$ls180.v:2708$4004 assign { } { } assign $1\builder_state[1:0] 2'00 sync always @@ -289980,7 +290006,7 @@ module \ls180 update \builder_state $1\builder_state[1:0] end attribute \src "ls180.v:2709.11-2709.36" - process $proc$ls180.v:2709$4003 + process $proc$ls180.v:2709$4005 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always @@ -289988,7 +290014,7 @@ module \ls180 update \builder_next_state $1\builder_next_state[1:0] end attribute \src "ls180.v:2710.11-2710.55" - process $proc$ls180.v:2710$4004 + process $proc$ls180.v:2710$4006 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always @@ -289996,7 +290022,7 @@ module \ls180 update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end attribute \src "ls180.v:2711.5-2711.52" - process $proc$ls180.v:2711$4005 + process $proc$ls180.v:2711$4007 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always @@ -290004,7 +290030,7 @@ module \ls180 update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end attribute \src "ls180.v:2712.12-2712.55" - process $proc$ls180.v:2712$4006 + process $proc$ls180.v:2712$4008 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always @@ -290012,7 +290038,7 @@ module \ls180 update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end attribute \src "ls180.v:2713.5-2713.50" - process $proc$ls180.v:2713$4007 + process $proc$ls180.v:2713$4009 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always @@ -290020,7 +290046,7 @@ module \ls180 update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end attribute \src "ls180.v:2714.5-2714.46" - process $proc$ls180.v:2714$4008 + process $proc$ls180.v:2714$4010 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always @@ -290028,7 +290054,7 @@ module \ls180 update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end attribute \src "ls180.v:2715.5-2715.49" - process $proc$ls180.v:2715$4009 + process $proc$ls180.v:2715$4011 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always @@ -290036,7 +290062,7 @@ module \ls180 update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4010 + process $proc$ls180.v:2716$4012 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always @@ -290044,7 +290070,7 @@ module \ls180 update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end attribute \src "ls180.v:2717.12-2717.49" - process $proc$ls180.v:2717$4011 + process $proc$ls180.v:2717$4013 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always @@ -290052,7 +290078,7 @@ module \ls180 update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end attribute \src "ls180.v:2718.11-2718.47" - process $proc$ls180.v:2718$4012 + process $proc$ls180.v:2718$4014 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always @@ -290060,7 +290086,7 @@ module \ls180 update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end attribute \src "ls180.v:2719.5-2719.41" - process $proc$ls180.v:2719$4013 + process $proc$ls180.v:2719$4015 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always @@ -290068,7 +290094,7 @@ module \ls180 update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end attribute \src "ls180.v:2720.5-2720.41" - process $proc$ls180.v:2720$4014 + process $proc$ls180.v:2720$4016 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always @@ -290076,7 +290102,7 @@ module \ls180 update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end attribute \src "ls180.v:2721.5-2721.41" - process $proc$ls180.v:2721$4015 + process $proc$ls180.v:2721$4017 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always @@ -290084,7 +290110,7 @@ module \ls180 update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end attribute \src "ls180.v:2722.5-2722.39" - process $proc$ls180.v:2722$4016 + process $proc$ls180.v:2722$4018 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always @@ -290092,7 +290118,7 @@ module \ls180 update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end attribute \src "ls180.v:2723.5-2723.39" - process $proc$ls180.v:2723$4017 + process $proc$ls180.v:2723$4019 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always @@ -290100,7 +290126,7 @@ module \ls180 update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end attribute \src "ls180.v:2724.5-2724.39" - process $proc$ls180.v:2724$4018 + process $proc$ls180.v:2724$4020 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always @@ -290108,7 +290134,7 @@ module \ls180 update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4019 + process $proc$ls180.v:2725$4021 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always @@ -290116,7 +290142,7 @@ module \ls180 update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end attribute \src "ls180.v:2726.12-2726.49" - process $proc$ls180.v:2726$4020 + process $proc$ls180.v:2726$4022 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always @@ -290124,7 +290150,7 @@ module \ls180 update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end attribute \src "ls180.v:2727.11-2727.47" - process $proc$ls180.v:2727$4021 + process $proc$ls180.v:2727$4023 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always @@ -290132,7 +290158,7 @@ module \ls180 update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end attribute \src "ls180.v:2728.5-2728.41" - process $proc$ls180.v:2728$4022 + process $proc$ls180.v:2728$4024 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always @@ -290140,7 +290166,7 @@ module \ls180 update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end attribute \src "ls180.v:2729.5-2729.42" - process $proc$ls180.v:2729$4023 + process $proc$ls180.v:2729$4025 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always @@ -290148,7 +290174,7 @@ module \ls180 update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end attribute \src "ls180.v:2730.5-2730.42" - process $proc$ls180.v:2730$4024 + process $proc$ls180.v:2730$4026 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always @@ -290156,7 +290182,7 @@ module \ls180 update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end attribute \src "ls180.v:2731.5-2731.39" - process $proc$ls180.v:2731$4025 + process $proc$ls180.v:2731$4027 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always @@ -290164,7 +290190,7 @@ module \ls180 update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end attribute \src "ls180.v:2732.5-2732.39" - process $proc$ls180.v:2732$4026 + process $proc$ls180.v:2732$4028 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always @@ -290172,7 +290198,7 @@ module \ls180 update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end attribute \src "ls180.v:2733.5-2733.39" - process $proc$ls180.v:2733$4027 + process $proc$ls180.v:2733$4029 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always @@ -290180,7 +290206,7 @@ module \ls180 update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4028 + process $proc$ls180.v:2734$4030 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always @@ -290188,7 +290214,7 @@ module \ls180 update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4029 + process $proc$ls180.v:2735$4031 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always @@ -290196,7 +290222,7 @@ module \ls180 update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4030 + process $proc$ls180.v:2736$4032 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always @@ -290204,7 +290230,7 @@ module \ls180 update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4031 + process $proc$ls180.v:2737$4033 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always @@ -290212,7 +290238,7 @@ module \ls180 update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4032 + process $proc$ls180.v:2738$4034 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always @@ -290220,7 +290246,7 @@ module \ls180 update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4033 + process $proc$ls180.v:2739$4035 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always @@ -290228,7 +290254,7 @@ module \ls180 update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end attribute \src "ls180.v:274.5-274.39" - process $proc$ls180.v:274$3177 + process $proc$ls180.v:274$3179 assign { } { } assign $0\main_interface1_ram_bus_err[0:0] 1'0 sync always @@ -290236,7 +290262,7 @@ module \ls180 sync init end attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4034 + process $proc$ls180.v:2740$4036 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always @@ -290244,7 +290270,7 @@ module \ls180 update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4035 + process $proc$ls180.v:2741$4037 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always @@ -290252,7 +290278,7 @@ module \ls180 update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4036 + process $proc$ls180.v:2742$4038 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always @@ -290260,7 +290286,7 @@ module \ls180 update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4037 + process $proc$ls180.v:2743$4039 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always @@ -290268,7 +290294,7 @@ module \ls180 update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end attribute \src "ls180.v:2744.5-2744.42" - process $proc$ls180.v:2744$4038 + process $proc$ls180.v:2744$4040 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always @@ -290276,7 +290302,7 @@ module \ls180 update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end attribute \src "ls180.v:2745.5-2745.42" - process $proc$ls180.v:2745$4039 + process $proc$ls180.v:2745$4041 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always @@ -290284,7 +290310,7 @@ module \ls180 update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end attribute \src "ls180.v:2746.12-2746.50" - process $proc$ls180.v:2746$4040 + process $proc$ls180.v:2746$4042 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always @@ -290292,7 +290318,7 @@ module \ls180 update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end attribute \src "ls180.v:2747.12-2747.50" - process $proc$ls180.v:2747$4041 + process $proc$ls180.v:2747$4043 assign { } { } assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -290300,7 +290326,7 @@ module \ls180 update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end attribute \src "ls180.v:2748.11-2748.48" - process $proc$ls180.v:2748$4042 + process $proc$ls180.v:2748$4044 assign { } { } assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always @@ -290308,7 +290334,7 @@ module \ls180 update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end attribute \src "ls180.v:2749.5-2749.42" - process $proc$ls180.v:2749$4043 + process $proc$ls180.v:2749$4045 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always @@ -290316,7 +290342,7 @@ module \ls180 update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end attribute \src "ls180.v:2750.5-2750.42" - process $proc$ls180.v:2750$4044 + process $proc$ls180.v:2750$4046 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always @@ -290324,7 +290350,7 @@ module \ls180 update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end attribute \src "ls180.v:2751.5-2751.42" - process $proc$ls180.v:2751$4045 + process $proc$ls180.v:2751$4047 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always @@ -290332,7 +290358,7 @@ module \ls180 update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end attribute \src "ls180.v:2752.11-2752.48" - process $proc$ls180.v:2752$4046 + process $proc$ls180.v:2752$4048 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always @@ -290340,7 +290366,7 @@ module \ls180 update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end attribute \src "ls180.v:2753.11-2753.48" - process $proc$ls180.v:2753$4047 + process $proc$ls180.v:2753$4049 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always @@ -290348,7 +290374,7 @@ module \ls180 update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end attribute \src "ls180.v:2754.11-2754.47" - process $proc$ls180.v:2754$4048 + process $proc$ls180.v:2754$4050 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always @@ -290356,7 +290382,7 @@ module \ls180 update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end attribute \src "ls180.v:2755.12-2755.49" - process $proc$ls180.v:2755$4049 + process $proc$ls180.v:2755$4051 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always @@ -290364,7 +290390,7 @@ module \ls180 update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4050 + process $proc$ls180.v:2756$4052 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always @@ -290372,7 +290398,7 @@ module \ls180 update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4051 + process $proc$ls180.v:2757$4053 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always @@ -290380,7 +290406,7 @@ module \ls180 update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end attribute \src "ls180.v:2758.5-2758.41" - process $proc$ls180.v:2758$4052 + process $proc$ls180.v:2758$4054 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always @@ -290388,7 +290414,7 @@ module \ls180 update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end attribute \src "ls180.v:2759.5-2759.41" - process $proc$ls180.v:2759$4053 + process $proc$ls180.v:2759$4055 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always @@ -290396,7 +290422,7 @@ module \ls180 update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end attribute \src "ls180.v:2760.5-2760.41" - process $proc$ls180.v:2760$4054 + process $proc$ls180.v:2760$4056 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always @@ -290404,7 +290430,7 @@ module \ls180 update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end attribute \src "ls180.v:2761.5-2761.39" - process $proc$ls180.v:2761$4055 + process $proc$ls180.v:2761$4057 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always @@ -290412,7 +290438,7 @@ module \ls180 update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end attribute \src "ls180.v:2762.5-2762.39" - process $proc$ls180.v:2762$4056 + process $proc$ls180.v:2762$4058 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always @@ -290420,7 +290446,7 @@ module \ls180 update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end attribute \src "ls180.v:277.11-277.31" - process $proc$ls180.v:277$3178 + process $proc$ls180.v:277$3180 assign { } { } assign $1\main_sram1_we[7:0] 8'00000000 sync always @@ -290428,7 +290454,7 @@ module \ls180 update \main_sram1_we $1\main_sram1_we[7:0] end attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4057 + process $proc$ls180.v:2819$4059 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always @@ -290436,7 +290462,7 @@ module \ls180 update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4058 + process $proc$ls180.v:2820$4060 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always @@ -290444,7 +290470,7 @@ module \ls180 update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4059 + process $proc$ls180.v:2821$4061 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always @@ -290452,7 +290478,7 @@ module \ls180 update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4060 + process $proc$ls180.v:2822$4062 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always @@ -290460,7 +290486,7 @@ module \ls180 update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4061 + process $proc$ls180.v:2823$4063 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always @@ -290468,7 +290494,7 @@ module \ls180 update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4062 + process $proc$ls180.v:2824$4064 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always @@ -290476,7 +290502,7 @@ module \ls180 update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4063 + process $proc$ls180.v:2825$4065 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always @@ -290484,7 +290510,7 @@ module \ls180 update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4064 + process $proc$ls180.v:2826$4066 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always @@ -290492,7 +290518,7 @@ module \ls180 update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4065 + process $proc$ls180.v:2827$4067 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always @@ -290500,7 +290526,7 @@ module \ls180 update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4066 + process $proc$ls180.v:2828$4068 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always @@ -290508,7 +290534,7 @@ module \ls180 update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4067 + process $proc$ls180.v:2829$4069 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always @@ -290516,7 +290542,7 @@ module \ls180 update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4068 + process $proc$ls180.v:2830$4070 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always @@ -290524,7 +290550,7 @@ module \ls180 update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4069 + process $proc$ls180.v:2831$4071 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always @@ -290532,7 +290558,7 @@ module \ls180 update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4070 + process $proc$ls180.v:2832$4072 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always @@ -290540,7 +290566,7 @@ module \ls180 update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4071 + process $proc$ls180.v:2833$4073 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always @@ -290548,7 +290574,7 @@ module \ls180 update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4072 + process $proc$ls180.v:2834$4074 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always @@ -290556,7 +290582,7 @@ module \ls180 update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4073 + process $proc$ls180.v:2835$4075 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always @@ -290564,7 +290590,7 @@ module \ls180 update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end attribute \src "ls180.v:2836.32-2836.66" - process $proc$ls180.v:2836$4074 + process $proc$ls180.v:2836$4076 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always @@ -290572,7 +290598,7 @@ module \ls180 update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end attribute \src "ls180.v:2837.32-2837.66" - process $proc$ls180.v:2837$4075 + process $proc$ls180.v:2837$4077 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always @@ -290580,7 +290606,7 @@ module \ls180 update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end attribute \src "ls180.v:2838.32-2838.66" - process $proc$ls180.v:2838$4076 + process $proc$ls180.v:2838$4078 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always @@ -290588,7 +290614,7 @@ module \ls180 update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4077 + process $proc$ls180.v:2839$4079 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always @@ -290596,7 +290622,7 @@ module \ls180 update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4078 + process $proc$ls180.v:2840$4080 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always @@ -290604,7 +290630,7 @@ module \ls180 update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4079 + process $proc$ls180.v:2841$4081 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always @@ -290612,7 +290638,7 @@ module \ls180 update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4080 + process $proc$ls180.v:2842$4082 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always @@ -290620,7 +290646,7 @@ module \ls180 update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4081 + process $proc$ls180.v:2843$4083 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always @@ -290628,7 +290654,7 @@ module \ls180 update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4082 + process $proc$ls180.v:2844$4084 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always @@ -290636,7 +290662,7 @@ module \ls180 update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4083 + process $proc$ls180.v:2845$4085 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always @@ -290644,7 +290670,7 @@ module \ls180 update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4084 + process $proc$ls180.v:2846$4086 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always @@ -290652,7 +290678,7 @@ module \ls180 update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4085 + process $proc$ls180.v:2847$4087 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always @@ -290660,7 +290686,7 @@ module \ls180 update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4086 + process $proc$ls180.v:2848$4088 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always @@ -290668,7 +290694,7 @@ module \ls180 update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4087 + process $proc$ls180.v:2849$4089 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always @@ -290676,7 +290702,7 @@ module \ls180 update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$3179 + process $proc$ls180.v:285$3181 assign { } { } assign $1\main_interface2_ram_bus_ack[0:0] 1'0 sync always @@ -290684,7 +290710,7 @@ module \ls180 update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] end attribute \src "ls180.v:2850.32-2850.67" - process $proc$ls180.v:2850$4088 + process $proc$ls180.v:2850$4090 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always @@ -290692,7 +290718,7 @@ module \ls180 update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end attribute \src "ls180.v:2851.32-2851.67" - process $proc$ls180.v:2851$4089 + process $proc$ls180.v:2851$4091 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always @@ -290700,7 +290726,7 @@ module \ls180 update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end attribute \src "ls180.v:2852.32-2852.67" - process $proc$ls180.v:2852$4090 + process $proc$ls180.v:2852$4092 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always @@ -290718,7 +290744,7 @@ module \ls180 update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:289.5-289.39" - process $proc$ls180.v:289$3180 + process $proc$ls180.v:289$3182 assign { } { } assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always @@ -290831,7 +290857,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end attribute \src "ls180.v:292.11-292.31" - process $proc$ls180.v:292$3181 + process $proc$ls180.v:292$3183 assign { } { } assign $1\main_sram2_we[7:0] 8'00000000 sync always @@ -290868,10 +290894,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 @@ -290944,7 +290970,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end attribute \src "ls180.v:300.5-300.39" - process $proc$ls180.v:300$3182 + process $proc$ls180.v:300$3184 assign { } { } assign $1\main_interface3_ram_bus_ack[0:0] 1'0 sync always @@ -290980,8 +291006,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_we[0:0] 1'0 assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 assign $0\main_wb_sdram_sel[3:0] 4'0000 @@ -290989,7 +291016,6 @@ module \ls180 assign $0\main_wb_sdram_stb[0:0] 1'0 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state @@ -291057,7 +291083,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end attribute \src "ls180.v:304.5-304.39" - process $proc$ls180.v:304$3183 + process $proc$ls180.v:304$3185 assign { } { } assign $0\main_interface3_ram_bus_err[0:0] 1'0 sync always @@ -291065,7 +291091,7 @@ module \ls180 sync init end attribute \src "ls180.v:307.11-307.31" - process $proc$ls180.v:307$3184 + process $proc$ls180.v:307$3186 assign { } { } assign $1\main_sram3_we[7:0] 8'00000000 sync always @@ -291162,7 +291188,7 @@ module \ls180 update \main_sram3_we $0\main_sram3_we[7:0] end attribute \src "ls180.v:315.5-315.51" - process $proc$ls180.v:315$3185 + process $proc$ls180.v:315$3187 assign { } { } assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always @@ -291170,7 +291196,7 @@ module \ls180 update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end attribute \src "ls180.v:319.5-319.51" - process $proc$ls180.v:319$3186 + process $proc$ls180.v:319$3188 assign { } { } assign $0\main_interface0_converted_interface_err[0:0] 1'0 sync always @@ -291275,7 +291301,7 @@ module \ls180 update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end attribute \src "ls180.v:320.5-320.32" - process $proc$ls180.v:320$3187 + process $proc$ls180.v:320$3189 assign { } { } assign $1\main_converter0_skip[0:0] 1'0 sync always @@ -291283,7 +291309,7 @@ module \ls180 update \main_converter0_skip $1\main_converter0_skip[0:0] end attribute \src "ls180.v:321.5-321.35" - process $proc$ls180.v:321$3188 + process $proc$ls180.v:321$3190 assign { } { } assign $1\main_converter0_counter[0:0] 1'0 sync always @@ -291291,7 +291317,7 @@ module \ls180 update \main_converter0_counter $1\main_converter0_counter[0:0] end attribute \src "ls180.v:323.12-323.41" - process $proc$ls180.v:323$3189 + process $proc$ls180.v:323$3191 assign { } { } assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -291304,10 +291330,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re attribute \src "ls180.v:3254.6-3254.33" @@ -291330,7 +291356,7 @@ module \ls180 update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end attribute \src "ls180.v:330.5-330.51" - process $proc$ls180.v:330$3190 + process $proc$ls180.v:330$3192 assign { } { } assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always @@ -291343,10 +291369,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state @@ -291396,7 +291422,7 @@ module \ls180 update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end attribute \src "ls180.v:334.5-334.51" - process $proc$ls180.v:334$3191 + process $proc$ls180.v:334$3193 assign { } { } assign $0\main_interface1_converted_interface_err[0:0] 1'0 sync always @@ -291404,7 +291430,7 @@ module \ls180 sync init end attribute \src "ls180.v:335.5-335.32" - process $proc$ls180.v:335$3192 + process $proc$ls180.v:335$3194 assign { } { } assign $1\main_converter1_skip[0:0] 1'0 sync always @@ -291428,7 +291454,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:336.5-336.35" - process $proc$ls180.v:336$3193 + process $proc$ls180.v:336$3195 assign { } { } assign $1\main_converter1_counter[0:0] 1'0 sync always @@ -291456,7 +291482,7 @@ module \ls180 update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end attribute \src "ls180.v:338.12-338.41" - process $proc$ls180.v:338$3194 + process $proc$ls180.v:338$3196 assign { } { } assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -291657,7 +291683,7 @@ module \ls180 update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end attribute \src "ls180.v:342.5-342.24" - process $proc$ls180.v:342$3195 + process $proc$ls180.v:342$3197 assign { } { } assign $1\main_int_rst[0:0] 1'1 sync always @@ -291894,7 +291920,7 @@ module \ls180 update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end attribute \src "ls180.v:357.12-357.38" - process $proc$ls180.v:357$3196 + process $proc$ls180.v:357$3198 assign { } { } assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 sync always @@ -291902,7 +291928,7 @@ module \ls180 update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end attribute \src "ls180.v:358.5-358.36" - process $proc$ls180.v:358$3197 + process $proc$ls180.v:358$3199 assign { } { } assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 sync always @@ -291910,7 +291936,7 @@ module \ls180 update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end attribute \src "ls180.v:359.11-359.32" - process $proc$ls180.v:359$3198 + process $proc$ls180.v:359$3200 assign { } { } assign $1\main_rddata_en[2:0] 3'000 sync always @@ -291918,7 +291944,7 @@ module \ls180 update \main_rddata_en $1\main_rddata_en[2:0] end attribute \src "ls180.v:362.5-362.36" - process $proc$ls180.v:362$3199 + process $proc$ls180.v:362$3201 assign { } { } assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always @@ -291926,7 +291952,7 @@ module \ls180 update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end attribute \src "ls180.v:363.5-363.35" - process $proc$ls180.v:363$3200 + process $proc$ls180.v:363$3202 assign { } { } assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 sync always @@ -291934,7 +291960,7 @@ module \ls180 update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end attribute \src "ls180.v:364.5-364.36" - process $proc$ls180.v:364$3201 + process $proc$ls180.v:364$3203 assign { } { } assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always @@ -291942,7 +291968,7 @@ module \ls180 update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end attribute \src "ls180.v:365.5-365.35" - process $proc$ls180.v:365$3202 + process $proc$ls180.v:365$3204 assign { } { } assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always @@ -291986,7 +292012,7 @@ module \ls180 update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end attribute \src "ls180.v:369.5-369.36" - process $proc$ls180.v:369$3203 + process $proc$ls180.v:369$3205 assign { } { } assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always @@ -292025,6 +292051,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 @@ -292033,12 +292060,11 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state @@ -292187,7 +292213,7 @@ module \ls180 update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end attribute \src "ls180.v:374.12-374.45" - process $proc$ls180.v:374$3204 + process $proc$ls180.v:374$3206 assign { } { } assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always @@ -292195,7 +292221,7 @@ module \ls180 update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end attribute \src "ls180.v:375.5-375.43" - process $proc$ls180.v:375$3205 + process $proc$ls180.v:375$3207 assign { } { } assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always @@ -292270,6 +292296,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 @@ -292283,7 +292310,6 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state @@ -292432,7 +292458,7 @@ module \ls180 update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end attribute \src "ls180.v:390.12-390.46" - process $proc$ls180.v:390$3206 + process $proc$ls180.v:390$3208 assign { } { } assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always @@ -292440,7 +292466,7 @@ module \ls180 update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end attribute \src "ls180.v:391.5-391.44" - process $proc$ls180.v:391$3207 + process $proc$ls180.v:391$3209 assign { } { } assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always @@ -292448,7 +292474,7 @@ module \ls180 update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end attribute \src "ls180.v:392.12-392.48" - process $proc$ls180.v:392$3208 + process $proc$ls180.v:392$3210 assign { } { } assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always @@ -292456,7 +292482,7 @@ module \ls180 update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end attribute \src "ls180.v:393.11-393.43" - process $proc$ls180.v:393$3209 + process $proc$ls180.v:393$3211 assign { } { } assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always @@ -292464,7 +292490,7 @@ module \ls180 update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end attribute \src "ls180.v:394.5-394.38" - process $proc$ls180.v:394$3210 + process $proc$ls180.v:394$3212 assign { } { } assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always @@ -292472,7 +292498,7 @@ module \ls180 update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end attribute \src "ls180.v:395.5-395.37" - process $proc$ls180.v:395$3211 + process $proc$ls180.v:395$3213 assign { } { } assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always @@ -292480,7 +292506,7 @@ module \ls180 update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end attribute \src "ls180.v:396.5-396.38" - process $proc$ls180.v:396$3212 + process $proc$ls180.v:396$3214 assign { } { } assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always @@ -292488,7 +292514,7 @@ module \ls180 update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end attribute \src "ls180.v:397.5-397.37" - process $proc$ls180.v:397$3213 + process $proc$ls180.v:397$3215 assign { } { } assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always @@ -292496,7 +292522,7 @@ module \ls180 update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end attribute \src "ls180.v:398.5-398.36" - process $proc$ls180.v:398$3214 + process $proc$ls180.v:398$3216 assign { } { } assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always @@ -292515,7 +292541,7 @@ module \ls180 update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:399.5-399.36" - process $proc$ls180.v:399$3215 + process $proc$ls180.v:399$3217 assign { } { } assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always @@ -292523,7 +292549,7 @@ module \ls180 update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end attribute \src "ls180.v:400.5-400.40" - process $proc$ls180.v:400$3216 + process $proc$ls180.v:400$3218 assign { } { } assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 sync always @@ -292559,7 +292585,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:401.5-401.38" - process $proc$ls180.v:401$3217 + process $proc$ls180.v:401$3219 assign { } { } assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always @@ -292592,7 +292618,7 @@ module \ls180 update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end attribute \src "ls180.v:402.12-402.47" - process $proc$ls180.v:402$3218 + process $proc$ls180.v:402$3220 assign { } { } assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always @@ -292600,7 +292626,7 @@ module \ls180 update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end attribute \src "ls180.v:403.5-403.42" - process $proc$ls180.v:403$3219 + process $proc$ls180.v:403$3221 assign { } { } assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 sync always @@ -292636,7 +292662,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:404.11-404.50" - process $proc$ls180.v:404$3220 + process $proc$ls180.v:404$3222 assign { } { } assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 sync always @@ -292658,7 +292684,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:405.5-405.42" - process $proc$ls180.v:405$3221 + process $proc$ls180.v:405$3223 assign { } { } assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 sync always @@ -292760,15 +292786,15 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdram_en1[0:0] 1'0 assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state attribute \src "ls180.v:4103.2-4162.9" @@ -292876,7 +292902,7 @@ module \ls180 update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end attribute \src "ls180.v:412.11-412.36" - process $proc$ls180.v:412$3222 + process $proc$ls180.v:412$3224 assign { } { } assign $1\main_sdram_storage[3:0] 4'0001 sync always @@ -292884,7 +292910,7 @@ module \ls180 update \main_sdram_storage $1\main_sdram_storage[3:0] end attribute \src "ls180.v:413.5-413.25" - process $proc$ls180.v:413$3223 + process $proc$ls180.v:413$3225 assign { } { } assign $1\main_sdram_re[0:0] 1'0 sync always @@ -292892,7 +292918,7 @@ module \ls180 update \main_sdram_re $1\main_sdram_re[0:0] end attribute \src "ls180.v:414.11-414.44" - process $proc$ls180.v:414$3224 + process $proc$ls180.v:414$3226 assign { } { } assign $1\main_sdram_command_storage[5:0] 6'000000 sync always @@ -292900,7 +292926,7 @@ module \ls180 update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end attribute \src "ls180.v:415.5-415.33" - process $proc$ls180.v:415$3225 + process $proc$ls180.v:415$3227 assign { } { } assign $1\main_sdram_command_re[0:0] 1'0 sync always @@ -292929,7 +292955,7 @@ module \ls180 update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end attribute \src "ls180.v:419.5-419.38" - process $proc$ls180.v:419$3226 + process $proc$ls180.v:419$3228 assign { } { } assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always @@ -292937,7 +292963,7 @@ module \ls180 sync init end attribute \src "ls180.v:420.12-420.46" - process $proc$ls180.v:420$3227 + process $proc$ls180.v:420$3229 assign { } { } assign $1\main_sdram_address_storage[12:0] 13'0000000000000 sync always @@ -292962,7 +292988,7 @@ module \ls180 update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end attribute \src "ls180.v:421.5-421.33" - process $proc$ls180.v:421$3228 + process $proc$ls180.v:421$3230 assign { } { } assign $1\main_sdram_address_re[0:0] 1'0 sync always @@ -293058,7 +293084,7 @@ module \ls180 update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end attribute \src "ls180.v:422.11-422.45" - process $proc$ls180.v:422$3229 + process $proc$ls180.v:422$3231 assign { } { } assign $1\main_sdram_baddress_storage[1:0] 2'00 sync always @@ -293066,7 +293092,7 @@ module \ls180 update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] end attribute \src "ls180.v:423.5-423.34" - process $proc$ls180.v:423$3230 + process $proc$ls180.v:423$3232 assign { } { } assign $1\main_sdram_baddress_re[0:0] 1'0 sync always @@ -293074,7 +293100,7 @@ module \ls180 update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] end attribute \src "ls180.v:424.12-424.45" - process $proc$ls180.v:424$3231 + process $proc$ls180.v:424$3233 assign { } { } assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 sync always @@ -293082,7 +293108,7 @@ module \ls180 update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] end attribute \src "ls180.v:425.5-425.32" - process $proc$ls180.v:425$3232 + process $proc$ls180.v:425$3234 assign { } { } assign $1\main_sdram_wrdata_re[0:0] 1'0 sync always @@ -293090,7 +293116,7 @@ module \ls180 update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] end attribute \src "ls180.v:426.12-426.37" - process $proc$ls180.v:426$3233 + process $proc$ls180.v:426$3235 assign { } { } assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always @@ -293294,6 +293320,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\main_spisdcard_clk_enable[0:0] 1'0 assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'0 @@ -293302,7 +293329,6 @@ module \ls180 assign $0\main_spisdcard_irq[0:0] 1'0 assign { } { } assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state attribute \src "ls180.v:4490.2-4526.9" switch \builder_spimaster1_state @@ -293408,7 +293434,7 @@ module \ls180 update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end attribute \src "ls180.v:456.12-456.46" - process $proc$ls180.v:456$3234 + process $proc$ls180.v:456$3236 assign { } { } assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always @@ -293416,7 +293442,7 @@ module \ls180 update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end attribute \src "ls180.v:457.11-457.47" - process $proc$ls180.v:457$3235 + process $proc$ls180.v:457$3237 assign { } { } assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always @@ -293433,6 +293459,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } @@ -293440,7 +293467,6 @@ module \ls180 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state @@ -293489,7 +293515,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end attribute \src "ls180.v:459.12-459.45" - process $proc$ls180.v:459$3236 + process $proc$ls180.v:459$3238 assign { } { } assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always @@ -293497,7 +293523,7 @@ module \ls180 update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end attribute \src "ls180.v:460.11-460.40" - process $proc$ls180.v:460$3237 + process $proc$ls180.v:460$3239 assign { } { } assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 sync always @@ -293505,7 +293531,7 @@ module \ls180 update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end attribute \src "ls180.v:461.5-461.35" - process $proc$ls180.v:461$3238 + process $proc$ls180.v:461$3240 assign { } { } assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always @@ -293513,7 +293539,7 @@ module \ls180 update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end attribute \src "ls180.v:462.5-462.34" - process $proc$ls180.v:462$3239 + process $proc$ls180.v:462$3241 assign { } { } assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 sync always @@ -293530,6 +293556,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 @@ -293537,7 +293564,6 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:4633.2-4698.9" switch \builder_sdphy_sdphycmdw_state @@ -293643,7 +293669,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end attribute \src "ls180.v:463.5-463.35" - process $proc$ls180.v:463$3240 + process $proc$ls180.v:463$3242 assign { } { } assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always @@ -293651,7 +293677,7 @@ module \ls180 update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end attribute \src "ls180.v:464.5-464.34" - process $proc$ls180.v:464$3241 + process $proc$ls180.v:464$3243 assign { } { } assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always @@ -293659,7 +293685,7 @@ module \ls180 update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end attribute \src "ls180.v:468.5-468.35" - process $proc$ls180.v:468$3242 + process $proc$ls180.v:468$3244 assign { } { } assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always @@ -293667,7 +293693,7 @@ module \ls180 sync init end attribute \src "ls180.v:470.5-470.39" - process $proc$ls180.v:470$3243 + process $proc$ls180.v:470$3245 assign { } { } assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always @@ -293675,7 +293701,7 @@ module \ls180 update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end attribute \src "ls180.v:472.5-472.39" - process $proc$ls180.v:472$3244 + process $proc$ls180.v:472$3246 assign { } { } assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always @@ -293852,7 +293878,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end attribute \src "ls180.v:475.5-475.32" - process $proc$ls180.v:475$3245 + process $proc$ls180.v:475$3247 assign { } { } assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always @@ -293860,7 +293886,7 @@ module \ls180 update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end attribute \src "ls180.v:476.5-476.32" - process $proc$ls180.v:476$3246 + process $proc$ls180.v:476$3248 assign { } { } assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always @@ -293868,7 +293894,7 @@ module \ls180 update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end attribute \src "ls180.v:477.5-477.31" - process $proc$ls180.v:477$3247 + process $proc$ls180.v:477$3249 assign { } { } assign $1\main_sdram_cmd_last[0:0] 1'0 sync always @@ -293876,7 +293902,7 @@ module \ls180 update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end attribute \src "ls180.v:478.12-478.44" - process $proc$ls180.v:478$3248 + process $proc$ls180.v:478$3250 assign { } { } assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -293884,7 +293910,7 @@ module \ls180 update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end attribute \src "ls180.v:479.11-479.43" - process $proc$ls180.v:479$3249 + process $proc$ls180.v:479$3251 assign { } { } assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always @@ -293892,7 +293918,7 @@ module \ls180 update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end attribute \src "ls180.v:480.5-480.38" - process $proc$ls180.v:480$3250 + process $proc$ls180.v:480$3252 assign { } { } assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always @@ -293900,7 +293926,7 @@ module \ls180 update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end attribute \src "ls180.v:481.5-481.38" - process $proc$ls180.v:481$3251 + process $proc$ls180.v:481$3253 assign { } { } assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always @@ -293908,7 +293934,7 @@ module \ls180 update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end attribute \src "ls180.v:482.5-482.37" - process $proc$ls180.v:482$3252 + process $proc$ls180.v:482$3254 assign { } { } assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always @@ -293916,7 +293942,7 @@ module \ls180 update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end attribute \src "ls180.v:483.5-483.42" - process $proc$ls180.v:483$3253 + process $proc$ls180.v:483$3255 assign { } { } assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 sync always @@ -293924,7 +293950,7 @@ module \ls180 sync init end attribute \src "ls180.v:484.5-484.43" - process $proc$ls180.v:484$3254 + process $proc$ls180.v:484$3256 assign { } { } assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always @@ -293939,12 +293965,12 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state @@ -294111,7 +294137,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end attribute \src "ls180.v:490.11-490.44" - process $proc$ls180.v:490$3255 + process $proc$ls180.v:490$3257 assign { } { } assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always @@ -294119,7 +294145,7 @@ module \ls180 update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end attribute \src "ls180.v:492.5-492.38" - process $proc$ls180.v:492$3256 + process $proc$ls180.v:492$3258 assign { } { } assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always @@ -294127,7 +294153,7 @@ module \ls180 update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end attribute \src "ls180.v:493.5-493.38" - process $proc$ls180.v:493$3257 + process $proc$ls180.v:493$3259 assign { } { } assign $1\main_sdram_postponer_count[0:0] 1'0 sync always @@ -294135,7 +294161,7 @@ module \ls180 update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end attribute \src "ls180.v:494.5-494.39" - process $proc$ls180.v:494$3258 + process $proc$ls180.v:494$3260 assign { } { } assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always @@ -294143,7 +294169,7 @@ module \ls180 update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end attribute \src "ls180.v:497.5-497.38" - process $proc$ls180.v:497$3259 + process $proc$ls180.v:497$3261 assign { } { } assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always @@ -294151,7 +294177,7 @@ module \ls180 update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end attribute \src "ls180.v:498.11-498.46" - process $proc$ls180.v:498$3260 + process $proc$ls180.v:498$3262 assign { } { } assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always @@ -294159,7 +294185,7 @@ module \ls180 update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end attribute \src "ls180.v:499.5-499.38" - process $proc$ls180.v:499$3261 + process $proc$ls180.v:499$3263 assign { } { } assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always @@ -294183,12 +294209,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 @@ -294197,7 +294224,6 @@ module \ls180 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state @@ -294350,7 +294376,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end attribute \src "ls180.v:505.5-505.51" - process $proc$ls180.v:505$3262 + process $proc$ls180.v:505$3264 assign { } { } assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always @@ -294358,7 +294384,7 @@ module \ls180 update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$3263 + process $proc$ls180.v:506$3265 assign { } { } assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always @@ -294366,7 +294392,7 @@ module \ls180 update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end attribute \src "ls180.v:508.5-508.47" - process $proc$ls180.v:508$3264 + process $proc$ls180.v:508$3266 assign { } { } assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always @@ -294374,7 +294400,7 @@ module \ls180 update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] end attribute \src "ls180.v:509.5-509.45" - process $proc$ls180.v:509$3265 + process $proc$ls180.v:509$3267 assign { } { } assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always @@ -294382,7 +294408,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end attribute \src "ls180.v:510.5-510.45" - process $proc$ls180.v:510$3266 + process $proc$ls180.v:510$3268 assign { } { } assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always @@ -294390,7 +294416,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end attribute \src "ls180.v:511.12-511.57" - process $proc$ls180.v:511$3267 + process $proc$ls180.v:511$3269 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -294398,7 +294424,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:513.5-513.51" - process $proc$ls180.v:513$3268 + process $proc$ls180.v:513$3270 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always @@ -294406,7 +294432,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end attribute \src "ls180.v:514.5-514.51" - process $proc$ls180.v:514$3269 + process $proc$ls180.v:514$3271 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always @@ -294414,7 +294440,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end attribute \src "ls180.v:515.5-515.50" - process $proc$ls180.v:515$3270 + process $proc$ls180.v:515$3272 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always @@ -294438,7 +294464,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end attribute \src "ls180.v:516.5-516.54" - process $proc$ls180.v:516$3271 + process $proc$ls180.v:516$3273 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -294446,7 +294472,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:517.5-517.55" - process $proc$ls180.v:517$3272 + process $proc$ls180.v:517$3274 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always @@ -294470,7 +294496,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end attribute \src "ls180.v:518.5-518.56" - process $proc$ls180.v:518$3273 + process $proc$ls180.v:518$3275 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always @@ -294494,7 +294520,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end attribute \src "ls180.v:519.5-519.50" - process $proc$ls180.v:519$3274 + process $proc$ls180.v:519$3276 assign { } { } assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always @@ -294550,6 +294576,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } @@ -294557,7 +294584,6 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 @@ -294665,7 +294691,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end attribute \src "ls180.v:522.5-522.67" - process $proc$ls180.v:522$3275 + process $proc$ls180.v:522$3277 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -294673,7 +294699,7 @@ module \ls180 sync init end attribute \src "ls180.v:523.5-523.66" - process $proc$ls180.v:523$3276 + process $proc$ls180.v:523$3278 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -294837,7 +294863,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end attribute \src "ls180.v:538.11-538.68" - process $proc$ls180.v:538$3277 + process $proc$ls180.v:538$3279 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -294861,7 +294887,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end attribute \src "ls180.v:539.5-539.64" - process $proc$ls180.v:539$3278 + process $proc$ls180.v:539$3280 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -294909,6 +294935,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -294947,7 +294974,6 @@ module \ls180 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state @@ -295219,7 +295245,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end attribute \src "ls180.v:540.11-540.70" - process $proc$ls180.v:540$3279 + process $proc$ls180.v:540$3281 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -295227,7 +295253,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:541.11-541.70" - process $proc$ls180.v:541$3280 + process $proc$ls180.v:541$3282 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -295235,7 +295261,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:542.11-542.73" - process $proc$ls180.v:542$3281 + process $proc$ls180.v:542$3283 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -295243,7 +295269,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$3126 + process $proc$ls180.v:55$3128 assign { } { } assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always @@ -295251,7 +295277,7 @@ module \ls180 update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$3127 + process $proc$ls180.v:56$3129 assign { } { } assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always @@ -295275,7 +295301,7 @@ module \ls180 update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end attribute \src "ls180.v:563.5-563.59" - process $proc$ls180.v:563$3282 + process $proc$ls180.v:563$3284 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -295354,7 +295380,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end attribute \src "ls180.v:565.5-565.59" - process $proc$ls180.v:565$3283 + process $proc$ls180.v:565$3285 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always @@ -295362,7 +295388,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:566.5-566.58" - process $proc$ls180.v:566$3284 + process $proc$ls180.v:566$3286 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always @@ -295370,7 +295396,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:567.5-567.64" - process $proc$ls180.v:567$3285 + process $proc$ls180.v:567$3287 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -295378,7 +295404,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:568.12-568.74" - process $proc$ls180.v:568$3286 + process $proc$ls180.v:568$3288 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -295386,7 +295412,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:569.12-569.47" - process $proc$ls180.v:569$3287 + process $proc$ls180.v:569$3289 assign { } { } assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 sync always @@ -295394,7 +295420,7 @@ module \ls180 update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$3128 + process $proc$ls180.v:57$3130 assign { } { } assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always @@ -295402,7 +295428,7 @@ module \ls180 update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end attribute \src "ls180.v:570.5-570.46" - process $proc$ls180.v:570$3288 + process $proc$ls180.v:570$3290 assign { } { } assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always @@ -295423,6 +295449,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 @@ -295431,10 +295459,8 @@ module \ls180 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:5719.2-5741.9" switch \builder_sdmem2blockdma_fsm_state @@ -295483,7 +295509,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end attribute \src "ls180.v:572.5-572.44" - process $proc$ls180.v:572$3289 + process $proc$ls180.v:572$3291 assign { } { } assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always @@ -295491,7 +295517,7 @@ module \ls180 update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end attribute \src "ls180.v:573.5-573.45" - process $proc$ls180.v:573$3290 + process $proc$ls180.v:573$3292 assign { } { } assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always @@ -295499,7 +295525,7 @@ module \ls180 update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end attribute \src "ls180.v:574.5-574.54" - process $proc$ls180.v:574$3291 + process $proc$ls180.v:574$3293 assign { } { } assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always @@ -295515,13 +295541,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign { } { } assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state @@ -295573,7 +295599,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end attribute \src "ls180.v:576.32-576.76" - process $proc$ls180.v:576$3292 + process $proc$ls180.v:576$3294 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always @@ -295581,7 +295607,7 @@ module \ls180 update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end attribute \src "ls180.v:577.11-577.55" - process $proc$ls180.v:577$3293 + process $proc$ls180.v:577$3295 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always @@ -295589,7 +295615,7 @@ module \ls180 update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end attribute \src "ls180.v:579.32-579.75" - process $proc$ls180.v:579$3294 + process $proc$ls180.v:579$3296 assign { } { } assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always @@ -295631,7 +295657,7 @@ module \ls180 update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$3129 + process $proc$ls180.v:58$3131 assign { } { } assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always @@ -295639,7 +295665,7 @@ module \ls180 update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end attribute \src "ls180.v:581.32-581.76" - process $proc$ls180.v:581$3295 + process $proc$ls180.v:581$3297 assign { } { } assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always @@ -295725,7 +295751,7 @@ module \ls180 update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end attribute \src "ls180.v:587.5-587.51" - process $proc$ls180.v:587$3296 + process $proc$ls180.v:587$3298 assign { } { } assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always @@ -295733,7 +295759,7 @@ module \ls180 update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$3297 + process $proc$ls180.v:588$3299 assign { } { } assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always @@ -295741,7 +295767,7 @@ module \ls180 update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end attribute \src "ls180.v:590.5-590.47" - process $proc$ls180.v:590$3298 + process $proc$ls180.v:590$3300 assign { } { } assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always @@ -295769,7 +295795,7 @@ module \ls180 update \builder_slave_sel $0\builder_slave_sel[12:0] end attribute \src "ls180.v:591.5-591.45" - process $proc$ls180.v:591$3299 + process $proc$ls180.v:591$3301 assign { } { } assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always @@ -295777,7 +295803,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] end attribute \src "ls180.v:592.5-592.45" - process $proc$ls180.v:592$3300 + process $proc$ls180.v:592$3302 assign { } { } assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always @@ -295785,7 +295811,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end attribute \src "ls180.v:593.12-593.57" - process $proc$ls180.v:593$3301 + process $proc$ls180.v:593$3303 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -295793,7 +295819,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end attribute \src "ls180.v:595.5-595.51" - process $proc$ls180.v:595$3302 + process $proc$ls180.v:595$3304 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always @@ -295801,7 +295827,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end attribute \src "ls180.v:596.5-596.51" - process $proc$ls180.v:596$3303 + process $proc$ls180.v:596$3305 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always @@ -295809,7 +295835,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end attribute \src "ls180.v:597.5-597.50" - process $proc$ls180.v:597$3304 + process $proc$ls180.v:597$3306 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always @@ -295817,7 +295843,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end attribute \src "ls180.v:598.5-598.54" - process $proc$ls180.v:598$3305 + process $proc$ls180.v:598$3307 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -295825,7 +295851,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:599.5-599.55" - process $proc$ls180.v:599$3306 + process $proc$ls180.v:599$3308 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always @@ -295833,7 +295859,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end attribute \src "ls180.v:600.5-600.56" - process $proc$ls180.v:600$3307 + process $proc$ls180.v:600$3309 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always @@ -295841,7 +295867,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end attribute \src "ls180.v:601.5-601.50" - process $proc$ls180.v:601$3308 + process $proc$ls180.v:601$3310 assign { } { } assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always @@ -295873,7 +295899,7 @@ module \ls180 update \builder_error $0\builder_error[0:0] end attribute \src "ls180.v:604.5-604.67" - process $proc$ls180.v:604$3309 + process $proc$ls180.v:604$3311 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -295881,7 +295907,7 @@ module \ls180 sync init end attribute \src "ls180.v:605.5-605.66" - process $proc$ls180.v:605$3310 + process $proc$ls180.v:605$3312 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -295889,7 +295915,7 @@ module \ls180 sync init end attribute \src "ls180.v:620.11-620.68" - process $proc$ls180.v:620$3311 + process $proc$ls180.v:620$3313 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -295897,7 +295923,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:621.5-621.64" - process $proc$ls180.v:621$3312 + process $proc$ls180.v:621$3314 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -295905,7 +295931,7 @@ module \ls180 sync init end attribute \src "ls180.v:622.11-622.70" - process $proc$ls180.v:622$3313 + process $proc$ls180.v:622$3315 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -295913,7 +295939,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:623.11-623.70" - process $proc$ls180.v:623$3314 + process $proc$ls180.v:623$3316 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -295921,7 +295947,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:624.11-624.73" - process $proc$ls180.v:624$3315 + process $proc$ls180.v:624$3317 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -295929,7 +295955,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$3130 + process $proc$ls180.v:63$3132 assign { } { } assign $1\main_libresocsim_bus_errors[31:0] 0 sync always @@ -295937,7 +295963,7 @@ module \ls180 update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end attribute \src "ls180.v:645.5-645.59" - process $proc$ls180.v:645$3316 + process $proc$ls180.v:645$3318 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -295945,7 +295971,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:647.5-647.59" - process $proc$ls180.v:647$3317 + process $proc$ls180.v:647$3319 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always @@ -295953,7 +295979,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:648.5-648.58" - process $proc$ls180.v:648$3318 + process $proc$ls180.v:648$3320 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always @@ -295961,7 +295987,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:649.5-649.64" - process $proc$ls180.v:649$3319 + process $proc$ls180.v:649$3321 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -295969,7 +295995,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3131 + process $proc$ls180.v:65$3133 assign { } { } assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always @@ -295977,7 +296003,7 @@ module \ls180 update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:650.12-650.74" - process $proc$ls180.v:650$3320 + process $proc$ls180.v:650$3322 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -295985,7 +296011,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:651.12-651.47" - process $proc$ls180.v:651$3321 + process $proc$ls180.v:651$3323 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always @@ -295993,7 +296019,7 @@ module \ls180 update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end attribute \src "ls180.v:652.5-652.46" - process $proc$ls180.v:652$3322 + process $proc$ls180.v:652$3324 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always @@ -296001,7 +296027,7 @@ module \ls180 update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end attribute \src "ls180.v:654.5-654.44" - process $proc$ls180.v:654$3323 + process $proc$ls180.v:654$3325 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always @@ -296009,7 +296035,7 @@ module \ls180 update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end attribute \src "ls180.v:655.5-655.45" - process $proc$ls180.v:655$3324 + process $proc$ls180.v:655$3326 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always @@ -296031,7 +296057,7 @@ module \ls180 update \main_spimaster9_start $0\main_spimaster9_start[0:0] end attribute \src "ls180.v:656.5-656.54" - process $proc$ls180.v:656$3325 + process $proc$ls180.v:656$3327 assign { } { } assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always @@ -296039,7 +296065,7 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:658.32-658.76" - process $proc$ls180.v:658$3326 + process $proc$ls180.v:658$3328 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always @@ -296047,7 +296073,7 @@ module \ls180 update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end attribute \src "ls180.v:659.11-659.55" - process $proc$ls180.v:659$3327 + process $proc$ls180.v:659$3329 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always @@ -296069,7 +296095,7 @@ module \ls180 update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end attribute \src "ls180.v:661.32-661.75" - process $proc$ls180.v:661$3328 + process $proc$ls180.v:661$3330 assign { } { } assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always @@ -296077,7 +296103,7 @@ module \ls180 sync init end attribute \src "ls180.v:663.32-663.76" - process $proc$ls180.v:663$3329 + process $proc$ls180.v:663$3331 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always @@ -296085,7 +296111,7 @@ module \ls180 sync init end attribute \src "ls180.v:669.5-669.51" - process $proc$ls180.v:669$3330 + process $proc$ls180.v:669$3332 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always @@ -296093,7 +296119,7 @@ module \ls180 update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$3331 + process $proc$ls180.v:670$3333 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always @@ -296101,7 +296127,7 @@ module \ls180 update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end attribute \src "ls180.v:672.5-672.47" - process $proc$ls180.v:672$3332 + process $proc$ls180.v:672$3334 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always @@ -296109,7 +296135,7 @@ module \ls180 update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end attribute \src "ls180.v:673.5-673.45" - process $proc$ls180.v:673$3333 + process $proc$ls180.v:673$3335 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always @@ -296117,7 +296143,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end attribute \src "ls180.v:674.5-674.45" - process $proc$ls180.v:674$3334 + process $proc$ls180.v:674$3336 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always @@ -296125,7 +296151,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end attribute \src "ls180.v:675.12-675.57" - process $proc$ls180.v:675$3335 + process $proc$ls180.v:675$3337 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -296133,7 +296159,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end attribute \src "ls180.v:677.5-677.51" - process $proc$ls180.v:677$3336 + process $proc$ls180.v:677$3338 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always @@ -296141,7 +296167,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end attribute \src "ls180.v:678.5-678.51" - process $proc$ls180.v:678$3337 + process $proc$ls180.v:678$3339 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always @@ -296149,7 +296175,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end attribute \src "ls180.v:679.5-679.50" - process $proc$ls180.v:679$3338 + process $proc$ls180.v:679$3340 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always @@ -296179,7 +296205,7 @@ module \ls180 update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end attribute \src "ls180.v:680.5-680.54" - process $proc$ls180.v:680$3339 + process $proc$ls180.v:680$3341 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -296209,7 +296235,7 @@ module \ls180 update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end attribute \src "ls180.v:681.5-681.55" - process $proc$ls180.v:681$3340 + process $proc$ls180.v:681$3342 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always @@ -296217,7 +296243,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end attribute \src "ls180.v:682.5-682.56" - process $proc$ls180.v:682$3341 + process $proc$ls180.v:682$3343 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always @@ -296247,7 +296273,7 @@ module \ls180 update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end attribute \src "ls180.v:683.5-683.50" - process $proc$ls180.v:683$3342 + process $proc$ls180.v:683$3344 assign { } { } assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always @@ -296299,7 +296325,7 @@ module \ls180 update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end attribute \src "ls180.v:686.5-686.67" - process $proc$ls180.v:686$3343 + process $proc$ls180.v:686$3345 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -296307,7 +296333,7 @@ module \ls180 sync init end attribute \src "ls180.v:687.5-687.66" - process $proc$ls180.v:687$3344 + process $proc$ls180.v:687$3346 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -296513,7 +296539,7 @@ module \ls180 update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end attribute \src "ls180.v:702.11-702.68" - process $proc$ls180.v:702$3345 + process $proc$ls180.v:702$3347 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -296543,7 +296569,7 @@ module \ls180 update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end attribute \src "ls180.v:703.5-703.64" - process $proc$ls180.v:703$3346 + process $proc$ls180.v:703$3348 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -296551,7 +296577,7 @@ module \ls180 sync init end attribute \src "ls180.v:704.11-704.70" - process $proc$ls180.v:704$3347 + process $proc$ls180.v:704$3349 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -296581,7 +296607,7 @@ module \ls180 update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end attribute \src "ls180.v:705.11-705.70" - process $proc$ls180.v:705$3348 + process $proc$ls180.v:705$3350 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -296589,7 +296615,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:706.11-706.73" - process $proc$ls180.v:706$3349 + process $proc$ls180.v:706$3351 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -296897,7 +296923,7 @@ module \ls180 update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end attribute \src "ls180.v:727.5-727.59" - process $proc$ls180.v:727$3350 + process $proc$ls180.v:727$3352 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -296930,7 +296956,7 @@ module \ls180 update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end attribute \src "ls180.v:729.5-729.59" - process $proc$ls180.v:729$3351 + process $proc$ls180.v:729$3353 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always @@ -296963,7 +296989,7 @@ module \ls180 update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end attribute \src "ls180.v:730.5-730.58" - process $proc$ls180.v:730$3352 + process $proc$ls180.v:730$3354 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always @@ -296971,7 +296997,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:731.5-731.64" - process $proc$ls180.v:731$3353 + process $proc$ls180.v:731$3355 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -297004,7 +297030,7 @@ module \ls180 update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end attribute \src "ls180.v:732.12-732.74" - process $proc$ls180.v:732$3354 + process $proc$ls180.v:732$3356 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -297012,7 +297038,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:733.12-733.47" - process $proc$ls180.v:733$3355 + process $proc$ls180.v:733$3357 assign { } { } assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always @@ -297045,7 +297071,7 @@ module \ls180 update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end attribute \src "ls180.v:734.5-734.46" - process $proc$ls180.v:734$3356 + process $proc$ls180.v:734$3358 assign { } { } assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always @@ -297075,7 +297101,7 @@ module \ls180 update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end attribute \src "ls180.v:736.5-736.44" - process $proc$ls180.v:736$3357 + process $proc$ls180.v:736$3359 assign { } { } assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always @@ -297083,7 +297109,7 @@ module \ls180 update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end attribute \src "ls180.v:737.5-737.45" - process $proc$ls180.v:737$3358 + process $proc$ls180.v:737$3360 assign { } { } assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always @@ -297113,7 +297139,7 @@ module \ls180 update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end attribute \src "ls180.v:738.5-738.54" - process $proc$ls180.v:738$3359 + process $proc$ls180.v:738$3361 assign { } { } assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always @@ -297143,7 +297169,7 @@ module \ls180 update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$3132 + process $proc$ls180.v:74$3134 assign { } { } assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 sync always @@ -297151,7 +297177,7 @@ module \ls180 sync init end attribute \src "ls180.v:740.32-740.76" - process $proc$ls180.v:740$3360 + process $proc$ls180.v:740$3362 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always @@ -297181,7 +297207,7 @@ module \ls180 update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end attribute \src "ls180.v:741.11-741.55" - process $proc$ls180.v:741$3361 + process $proc$ls180.v:741$3363 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always @@ -297211,7 +297237,7 @@ module \ls180 update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end attribute \src "ls180.v:743.32-743.75" - process $proc$ls180.v:743$3362 + process $proc$ls180.v:743$3364 assign { } { } assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always @@ -297241,7 +297267,7 @@ module \ls180 update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end attribute \src "ls180.v:745.32-745.76" - process $proc$ls180.v:745$3363 + process $proc$ls180.v:745$3365 assign { } { } assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always @@ -297305,7 +297331,7 @@ module \ls180 update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3133 + process $proc$ls180.v:75$3135 assign { } { } assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 sync always @@ -297347,7 +297373,7 @@ module \ls180 update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end attribute \src "ls180.v:751.5-751.51" - process $proc$ls180.v:751$3364 + process $proc$ls180.v:751$3366 assign { } { } assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always @@ -297355,7 +297381,7 @@ module \ls180 update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end attribute \src "ls180.v:752.5-752.51" - process $proc$ls180.v:752$3365 + process $proc$ls180.v:752$3367 assign { } { } assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always @@ -297363,7 +297389,7 @@ module \ls180 update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end attribute \src "ls180.v:754.5-754.47" - process $proc$ls180.v:754$3366 + process $proc$ls180.v:754$3368 assign { } { } assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always @@ -297371,7 +297397,7 @@ module \ls180 update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end attribute \src "ls180.v:755.5-755.45" - process $proc$ls180.v:755$3367 + process $proc$ls180.v:755$3369 assign { } { } assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always @@ -297379,7 +297405,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end attribute \src "ls180.v:756.5-756.45" - process $proc$ls180.v:756$3368 + process $proc$ls180.v:756$3370 assign { } { } assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always @@ -297387,7 +297413,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end attribute \src "ls180.v:757.12-757.57" - process $proc$ls180.v:757$3369 + process $proc$ls180.v:757$3371 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -297410,7 +297436,7 @@ module \ls180 update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end attribute \src "ls180.v:759.5-759.51" - process $proc$ls180.v:759$3370 + process $proc$ls180.v:759$3372 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always @@ -297433,7 +297459,7 @@ module \ls180 update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end attribute \src "ls180.v:760.5-760.51" - process $proc$ls180.v:760$3371 + process $proc$ls180.v:760$3373 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always @@ -297441,7 +297467,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end attribute \src "ls180.v:761.5-761.50" - process $proc$ls180.v:761$3372 + process $proc$ls180.v:761$3374 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always @@ -297449,7 +297475,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end attribute \src "ls180.v:762.5-762.54" - process $proc$ls180.v:762$3373 + process $proc$ls180.v:762$3375 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -297464,7 +297490,7 @@ module \ls180 update \main_int_rst $0\main_int_rst[0:0] end attribute \src "ls180.v:763.5-763.55" - process $proc$ls180.v:763$3374 + process $proc$ls180.v:763$3376 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always @@ -297545,10 +297571,10 @@ module \ls180 assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] - assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_dm[1:0] [0] $and$ls180.v:7687$2571_Y + assign $0\sdram_dm[1:0] [1] $and$ls180.v:7688$2572_Y assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2572_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2574_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -297562,11 +297588,6 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -297578,12 +297599,17 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end attribute \src "ls180.v:764.5-764.56" - process $proc$ls180.v:764$3375 + process $proc$ls180.v:764$3377 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always @@ -297591,7 +297617,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end attribute \src "ls180.v:765.5-765.50" - process $proc$ls180.v:765$3376 + process $proc$ls180.v:765$3378 assign { } { } assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always @@ -297599,7 +297625,7 @@ module \ls180 update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end attribute \src "ls180.v:768.5-768.67" - process $proc$ls180.v:768$3377 + process $proc$ls180.v:768$3379 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -297607,7 +297633,7 @@ module \ls180 sync init end attribute \src "ls180.v:769.5-769.66" - process $proc$ls180.v:769$3378 + process $proc$ls180.v:769$3380 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -297615,15 +297641,15 @@ module \ls180 sync init end attribute \src "ls180.v:7705.1-10349.4" - process $proc$ls180.v:7705$2573 - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } + process $proc$ls180.v:7705$2575 assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } - assign $0\uart_tx[0:0] \uart_tx assign $0\pwm[1:0] \pwm + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage @@ -298032,30 +298058,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2574_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2575_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2576_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2577_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2578_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2579_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2580_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2581_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2582_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2583_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2584_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2585_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2586_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2587_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2588_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2589_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2590_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2591_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2592_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2593_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2594_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2595_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2596_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2597_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2576_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2577_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2578_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2579_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2580_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2581_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2582_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2583_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2584_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2585_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2586_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2587_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2588_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2589_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2590_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2591_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2592_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2593_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2594_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2595_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2596_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2597_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2598_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2599_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -298082,14 +298108,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2706_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2707_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2708_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2708_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2709_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2710_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2726_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2738_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2728_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2740_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -298099,11 +298125,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2784_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2787_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2786_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2789_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2789_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2792_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2791_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2794_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -298215,7 +298241,7 @@ module \ls180 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 attribute \src "ls180.v:7730.2-7732.5" - switch $or$ls180.v:7730$2598_Y + switch $or$ls180.v:7730$2600_Y attribute \src "ls180.v:7730.6-7730.69" case 1'1 assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r @@ -298237,7 +298263,7 @@ module \ls180 case end attribute \src "ls180.v:7741.2-7743.5" - switch $or$ls180.v:7741$2599_Y + switch $or$ls180.v:7741$2601_Y attribute \src "ls180.v:7741.6-7741.69" case 1'1 assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r @@ -298259,7 +298285,7 @@ module \ls180 case end attribute \src "ls180.v:7752.2-7754.5" - switch $or$ls180.v:7752$2600_Y + switch $or$ls180.v:7752$2602_Y attribute \src "ls180.v:7752.6-7752.51" case 1'1 assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r @@ -298281,20 +298307,20 @@ module \ls180 case end attribute \src "ls180.v:7763.2-7767.5" - switch $ne$ls180.v:7763$2601_Y + switch $ne$ls180.v:7763$2603_Y attribute \src "ls180.v:7763.6-7763.53" case 1'1 attribute \src "ls180.v:7764.3-7766.6" switch \main_libresocsim_bus_error attribute \src "ls180.v:7764.7-7764.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2602_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2604_Y case end case end attribute \src "ls180.v:7769.2-7771.5" - switch $and$ls180.v:7769$2605_Y + switch $and$ls180.v:7769$2607_Y attribute \src "ls180.v:7769.6-7769.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 @@ -298305,13 +298331,13 @@ module \ls180 attribute \src "ls180.v:7772.6-7772.33" case 1'1 attribute \src "ls180.v:7773.3-7777.6" - switch $eq$ls180.v:7773$2606_Y + switch $eq$ls180.v:7773$2608_Y attribute \src "ls180.v:7773.7-7773.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage attribute \src "ls180.v:7775.7-7775.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2607_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2609_Y end attribute \src "ls180.v:7778.6-7778.10" case @@ -298332,35 +298358,35 @@ module \ls180 case end attribute \src "ls180.v:7788.2-7790.5" - switch $and$ls180.v:7788$2609_Y + switch $and$ls180.v:7788$2611_Y attribute \src "ls180.v:7788.6-7788.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end attribute \src "ls180.v:7792.2-7794.5" - switch $and$ls180.v:7792$2612_Y + switch $and$ls180.v:7792$2614_Y attribute \src "ls180.v:7792.6-7792.100" case 1'1 assign $0\main_interface0_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7796.2-7798.5" - switch $and$ls180.v:7796$2615_Y + switch $and$ls180.v:7796$2617_Y attribute \src "ls180.v:7796.6-7796.100" case 1'1 assign $0\main_interface1_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7800.2-7802.5" - switch $and$ls180.v:7800$2618_Y + switch $and$ls180.v:7800$2620_Y attribute \src "ls180.v:7800.6-7800.100" case 1'1 assign $0\main_interface2_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7804.2-7806.5" - switch $and$ls180.v:7804$2621_Y + switch $and$ls180.v:7804$2623_Y attribute \src "ls180.v:7804.6-7804.100" case 1'1 assign $0\main_interface3_ram_bus_ack[0:0] 1'1 @@ -298374,10 +298400,10 @@ module \ls180 case end attribute \src "ls180.v:7812.2-7816.5" - switch $and$ls180.v:7812$2623_Y + switch $and$ls180.v:7812$2625_Y attribute \src "ls180.v:7812.6-7812.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2624_Y + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2626_Y attribute \src "ls180.v:7814.6-7814.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 @@ -298386,9 +298412,9 @@ module \ls180 switch \main_sdram_postponer_req_i attribute \src "ls180.v:7818.6-7818.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2625_Y + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2627_Y attribute \src "ls180.v:7820.3-7823.6" - switch $eq$ls180.v:7820$2626_Y + switch $eq$ls180.v:7820$2628_Y attribute \src "ls180.v:7820.7-7820.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 @@ -298409,17 +298435,17 @@ module \ls180 attribute \src "ls180.v:7828.7-7828.33" case 1'1 attribute \src "ls180.v:7829.4-7831.7" - switch $ne$ls180.v:7829$2627_Y + switch $ne$ls180.v:7829$2629_Y attribute \src "ls180.v:7829.8-7829.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2628_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2630_Y case end case end end attribute \src "ls180.v:7840.2-7846.5" - switch $and$ls180.v:7840$2630_Y + switch $and$ls180.v:7840$2632_Y attribute \src "ls180.v:7840.6-7840.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 @@ -298430,7 +298456,7 @@ module \ls180 case end attribute \src "ls180.v:7847.2-7853.5" - switch $eq$ls180.v:7847$2631_Y + switch $eq$ls180.v:7847$2633_Y attribute \src "ls180.v:7847.6-7847.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 @@ -298441,7 +298467,7 @@ module \ls180 case end attribute \src "ls180.v:7854.2-7861.5" - switch $eq$ls180.v:7854$2632_Y + switch $eq$ls180.v:7854$2634_Y attribute \src "ls180.v:7854.6-7854.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 @@ -298453,17 +298479,17 @@ module \ls180 case end attribute \src "ls180.v:7862.2-7872.5" - switch $eq$ls180.v:7862$2633_Y + switch $eq$ls180.v:7862$2635_Y attribute \src "ls180.v:7862.6-7862.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 attribute \src "ls180.v:7864.6-7864.10" case attribute \src "ls180.v:7865.3-7871.6" - switch $ne$ls180.v:7865$2634_Y + switch $ne$ls180.v:7865$2636_Y attribute \src "ls180.v:7865.7-7865.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2635_Y + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2637_Y attribute \src "ls180.v:7867.7-7867.11" case attribute \src "ls180.v:7868.4-7870.7" @@ -298492,28 +298518,28 @@ module \ls180 end end attribute \src "ls180.v:7882.2-7884.5" - switch $and$ls180.v:7882$2638_Y + switch $and$ls180.v:7882$2640_Y attribute \src "ls180.v:7882.6-7882.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2639_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2641_Y case end attribute \src "ls180.v:7885.2-7887.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7885.6-7885.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2640_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2642_Y case end attribute \src "ls180.v:7888.2-7896.5" - switch $and$ls180.v:7888$2643_Y + switch $and$ls180.v:7888$2645_Y attribute \src "ls180.v:7888.6-7888.191" case 1'1 attribute \src "ls180.v:7889.3-7891.6" - switch $not$ls180.v:7889$2644_Y + switch $not$ls180.v:7889$2646_Y attribute \src "ls180.v:7889.7-7889.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2645_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2647_Y case end attribute \src "ls180.v:7892.6-7892.10" @@ -298522,12 +298548,12 @@ module \ls180 switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7893.7-7893.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2646_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2648_Y case end end attribute \src "ls180.v:7897.2-7903.5" - switch $or$ls180.v:7897$2648_Y + switch $or$ls180.v:7897$2650_Y attribute \src "ls180.v:7897.6-7897.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid @@ -298551,12 +298577,12 @@ module \ls180 attribute \src "ls180.v:7911.6-7911.10" case attribute \src "ls180.v:7912.3-7917.6" - switch $not$ls180.v:7912$2649_Y + switch $not$ls180.v:7912$2651_Y attribute \src "ls180.v:7912.7-7912.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2650_Y + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2652_Y attribute \src "ls180.v:7914.4-7916.7" - switch $eq$ls180.v:7914$2651_Y + switch $eq$ls180.v:7914$2653_Y attribute \src "ls180.v:7914.8-7914.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 @@ -298582,28 +298608,28 @@ module \ls180 end end attribute \src "ls180.v:7928.2-7930.5" - switch $and$ls180.v:7928$2654_Y + switch $and$ls180.v:7928$2656_Y attribute \src "ls180.v:7928.6-7928.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2655_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2657_Y case end attribute \src "ls180.v:7931.2-7933.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7931.6-7931.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2656_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2658_Y case end attribute \src "ls180.v:7934.2-7942.5" - switch $and$ls180.v:7934$2659_Y + switch $and$ls180.v:7934$2661_Y attribute \src "ls180.v:7934.6-7934.191" case 1'1 attribute \src "ls180.v:7935.3-7937.6" - switch $not$ls180.v:7935$2660_Y + switch $not$ls180.v:7935$2662_Y attribute \src "ls180.v:7935.7-7935.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2661_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2663_Y case end attribute \src "ls180.v:7938.6-7938.10" @@ -298612,12 +298638,12 @@ module \ls180 switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7939.7-7939.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2662_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2664_Y case end end attribute \src "ls180.v:7943.2-7949.5" - switch $or$ls180.v:7943$2664_Y + switch $or$ls180.v:7943$2666_Y attribute \src "ls180.v:7943.6-7943.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid @@ -298641,12 +298667,12 @@ module \ls180 attribute \src "ls180.v:7957.6-7957.10" case attribute \src "ls180.v:7958.3-7963.6" - switch $not$ls180.v:7958$2665_Y + switch $not$ls180.v:7958$2667_Y attribute \src "ls180.v:7958.7-7958.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2666_Y + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2668_Y attribute \src "ls180.v:7960.4-7962.7" - switch $eq$ls180.v:7960$2667_Y + switch $eq$ls180.v:7960$2669_Y attribute \src "ls180.v:7960.8-7960.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 @@ -298672,28 +298698,28 @@ module \ls180 end end attribute \src "ls180.v:7974.2-7976.5" - switch $and$ls180.v:7974$2670_Y + switch $and$ls180.v:7974$2672_Y attribute \src "ls180.v:7974.6-7974.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2671_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2673_Y case end attribute \src "ls180.v:7977.2-7979.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7977.6-7977.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2672_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2674_Y case end attribute \src "ls180.v:7980.2-7988.5" - switch $and$ls180.v:7980$2675_Y + switch $and$ls180.v:7980$2677_Y attribute \src "ls180.v:7980.6-7980.191" case 1'1 attribute \src "ls180.v:7981.3-7983.6" - switch $not$ls180.v:7981$2676_Y + switch $not$ls180.v:7981$2678_Y attribute \src "ls180.v:7981.7-7981.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2677_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2679_Y case end attribute \src "ls180.v:7984.6-7984.10" @@ -298702,12 +298728,12 @@ module \ls180 switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7985.7-7985.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2678_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2680_Y case end end attribute \src "ls180.v:7989.2-7995.5" - switch $or$ls180.v:7989$2680_Y + switch $or$ls180.v:7989$2682_Y attribute \src "ls180.v:7989.6-7989.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid @@ -298731,12 +298757,12 @@ module \ls180 attribute \src "ls180.v:8003.6-8003.10" case attribute \src "ls180.v:8004.3-8009.6" - switch $not$ls180.v:8004$2681_Y + switch $not$ls180.v:8004$2683_Y attribute \src "ls180.v:8004.7-8004.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2682_Y + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2684_Y attribute \src "ls180.v:8006.4-8008.7" - switch $eq$ls180.v:8006$2683_Y + switch $eq$ls180.v:8006$2685_Y attribute \src "ls180.v:8006.8-8006.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 @@ -298762,28 +298788,28 @@ module \ls180 end end attribute \src "ls180.v:8020.2-8022.5" - switch $and$ls180.v:8020$2686_Y + switch $and$ls180.v:8020$2688_Y attribute \src "ls180.v:8020.6-8020.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2687_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2689_Y case end attribute \src "ls180.v:8023.2-8025.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:8023.6-8023.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2688_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2690_Y case end attribute \src "ls180.v:8026.2-8034.5" - switch $and$ls180.v:8026$2691_Y + switch $and$ls180.v:8026$2693_Y attribute \src "ls180.v:8026.6-8026.191" case 1'1 attribute \src "ls180.v:8027.3-8029.6" - switch $not$ls180.v:8027$2692_Y + switch $not$ls180.v:8027$2694_Y attribute \src "ls180.v:8027.7-8027.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2693_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2695_Y case end attribute \src "ls180.v:8030.6-8030.10" @@ -298792,12 +298818,12 @@ module \ls180 switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:8031.7-8031.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2694_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2696_Y case end end attribute \src "ls180.v:8035.2-8041.5" - switch $or$ls180.v:8035$2696_Y + switch $or$ls180.v:8035$2698_Y attribute \src "ls180.v:8035.6-8035.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid @@ -298821,12 +298847,12 @@ module \ls180 attribute \src "ls180.v:8049.6-8049.10" case attribute \src "ls180.v:8050.3-8055.6" - switch $not$ls180.v:8050$2697_Y + switch $not$ls180.v:8050$2699_Y attribute \src "ls180.v:8050.7-8050.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2698_Y + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2700_Y attribute \src "ls180.v:8052.4-8054.7" - switch $eq$ls180.v:8052$2699_Y + switch $eq$ls180.v:8052$2701_Y attribute \src "ls180.v:8052.8-8052.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 @@ -298836,32 +298862,32 @@ module \ls180 end end attribute \src "ls180.v:8058.2-8064.5" - switch $not$ls180.v:8058$2700_Y + switch $not$ls180.v:8058$2702_Y attribute \src "ls180.v:8058.6-8058.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 attribute \src "ls180.v:8060.6-8060.10" case attribute \src "ls180.v:8061.3-8063.6" - switch $not$ls180.v:8061$2701_Y + switch $not$ls180.v:8061$2703_Y attribute \src "ls180.v:8061.7-8061.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2702_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2704_Y case end end attribute \src "ls180.v:8065.2-8071.5" - switch $not$ls180.v:8065$2703_Y + switch $not$ls180.v:8065$2705_Y attribute \src "ls180.v:8065.6-8065.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 attribute \src "ls180.v:8067.6-8067.10" case attribute \src "ls180.v:8068.3-8070.6" - switch $not$ls180.v:8068$2704_Y + switch $not$ls180.v:8068$2706_Y attribute \src "ls180.v:8068.7-8068.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2705_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2707_Y case end end @@ -299100,12 +299126,12 @@ module \ls180 attribute \src "ls180.v:8199.6-8199.10" case attribute \src "ls180.v:8200.3-8205.6" - switch $not$ls180.v:8200$2709_Y + switch $not$ls180.v:8200$2711_Y attribute \src "ls180.v:8200.7-8200.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2710_Y + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2712_Y attribute \src "ls180.v:8202.4-8204.7" - switch $eq$ls180.v:8202$2711_Y + switch $eq$ls180.v:8202$2713_Y attribute \src "ls180.v:8202.8-8202.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 @@ -299128,12 +299154,12 @@ module \ls180 attribute \src "ls180.v:8214.6-8214.10" case attribute \src "ls180.v:8215.3-8220.6" - switch $not$ls180.v:8215$2712_Y + switch $not$ls180.v:8215$2714_Y attribute \src "ls180.v:8215.7-8215.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2713_Y + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2715_Y attribute \src "ls180.v:8217.4-8219.7" - switch $eq$ls180.v:8217$2714_Y + switch $eq$ls180.v:8217$2716_Y attribute \src "ls180.v:8217.8-8217.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 @@ -299143,7 +299169,7 @@ module \ls180 end end attribute \src "ls180.v:8228.2-8230.5" - switch $or$ls180.v:8228$2739_Y + switch $or$ls180.v:8228$2741_Y attribute \src "ls180.v:8228.6-8228.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r @@ -299173,14 +299199,14 @@ module \ls180 attribute \src "ls180.v:8242.6-8242.10" case attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2740_Y + switch $and$ls180.v:8243$2742_Y attribute \src "ls180.v:8243.7-8243.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end attribute \src "ls180.v:8246.3-8248.6" - switch $and$ls180.v:8246$2741_Y + switch $and$ls180.v:8246$2743_Y attribute \src "ls180.v:8246.7-8246.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 @@ -299188,7 +299214,7 @@ module \ls180 end end attribute \src "ls180.v:8251.2-8272.5" - switch $and$ls180.v:8251$2745_Y + switch $and$ls180.v:8251$2747_Y attribute \src "ls180.v:8251.6-8251.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data @@ -299198,19 +299224,19 @@ module \ls180 attribute \src "ls180.v:8256.6-8256.10" case attribute \src "ls180.v:8257.3-8271.6" - switch $and$ls180.v:8257$2746_Y + switch $and$ls180.v:8257$2748_Y attribute \src "ls180.v:8257.7-8257.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2747_Y + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2749_Y attribute \src "ls180.v:8259.4-8270.7" - switch $eq$ls180.v:8259$2748_Y + switch $eq$ls180.v:8259$2750_Y attribute \src "ls180.v:8259.8-8259.43" case 1'1 assign $0\uart_tx[0:0] 1'1 attribute \src "ls180.v:8261.8-8261.12" case attribute \src "ls180.v:8262.5-8269.8" - switch $eq$ls180.v:8262$2749_Y + switch $eq$ls180.v:8262$2751_Y attribute \src "ls180.v:8262.9-8262.44" case 1'1 assign $0\uart_tx[0:0] 1'1 @@ -299229,17 +299255,17 @@ module \ls180 switch \main_uart_phy_tx_busy attribute \src "ls180.v:8273.6-8273.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2750_Y + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2752_Y attribute \src "ls180.v:8275.6-8275.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end attribute \src "ls180.v:8280.2-8304.5" - switch $not$ls180.v:8280$2751_Y + switch $not$ls180.v:8280$2753_Y attribute \src "ls180.v:8280.6-8280.30" case 1'1 attribute \src "ls180.v:8281.3-8284.6" - switch $and$ls180.v:8281$2753_Y + switch $and$ls180.v:8281$2755_Y attribute \src "ls180.v:8281.7-8281.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 @@ -299252,9 +299278,9 @@ module \ls180 switch \main_uart_phy_uart_clk_rxen attribute \src "ls180.v:8286.7-8286.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2754_Y + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2756_Y attribute \src "ls180.v:8288.4-8302.7" - switch $eq$ls180.v:8288$2755_Y + switch $eq$ls180.v:8288$2757_Y attribute \src "ls180.v:8288.8-8288.43" case 1'1 attribute \src "ls180.v:8289.5-8291.8" @@ -299267,7 +299293,7 @@ module \ls180 attribute \src "ls180.v:8292.8-8292.12" case attribute \src "ls180.v:8293.5-8301.8" - switch $eq$ls180.v:8293$2756_Y + switch $eq$ls180.v:8293$2758_Y attribute \src "ls180.v:8293.9-8293.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 @@ -299291,7 +299317,7 @@ module \ls180 switch \main_uart_phy_rx_busy attribute \src "ls180.v:8305.6-8305.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2757_Y + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2759_Y attribute \src "ls180.v:8307.6-8307.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 @@ -299304,7 +299330,7 @@ module \ls180 case end attribute \src "ls180.v:8314.2-8316.5" - switch $and$ls180.v:8314$2759_Y + switch $and$ls180.v:8314$2761_Y attribute \src "ls180.v:8314.6-8314.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 @@ -299318,7 +299344,7 @@ module \ls180 case end attribute \src "ls180.v:8321.2-8323.5" - switch $and$ls180.v:8321$2761_Y + switch $and$ls180.v:8321$2763_Y attribute \src "ls180.v:8321.6-8321.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 @@ -299340,28 +299366,28 @@ module \ls180 end end attribute \src "ls180.v:8331.2-8333.5" - switch $and$ls180.v:8331$2764_Y + switch $and$ls180.v:8331$2766_Y attribute \src "ls180.v:8331.6-8331.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2765_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2767_Y case end attribute \src "ls180.v:8334.2-8336.5" switch \main_uart_tx_fifo_do_read attribute \src "ls180.v:8334.6-8334.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2766_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2768_Y case end attribute \src "ls180.v:8337.2-8345.5" - switch $and$ls180.v:8337$2769_Y + switch $and$ls180.v:8337$2771_Y attribute \src "ls180.v:8337.6-8337.108" case 1'1 attribute \src "ls180.v:8338.3-8340.6" - switch $not$ls180.v:8338$2770_Y + switch $not$ls180.v:8338$2772_Y attribute \src "ls180.v:8338.7-8338.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2771_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2773_Y case end attribute \src "ls180.v:8341.6-8341.10" @@ -299370,7 +299396,7 @@ module \ls180 switch \main_uart_tx_fifo_do_read attribute \src "ls180.v:8342.7-8342.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2772_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2774_Y case end end @@ -299390,28 +299416,28 @@ module \ls180 end end attribute \src "ls180.v:8353.2-8355.5" - switch $and$ls180.v:8353$2775_Y + switch $and$ls180.v:8353$2777_Y attribute \src "ls180.v:8353.6-8353.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2776_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2778_Y case end attribute \src "ls180.v:8356.2-8358.5" switch \main_uart_rx_fifo_do_read attribute \src "ls180.v:8356.6-8356.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2777_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2779_Y case end attribute \src "ls180.v:8359.2-8367.5" - switch $and$ls180.v:8359$2780_Y + switch $and$ls180.v:8359$2782_Y attribute \src "ls180.v:8359.6-8359.108" case 1'1 attribute \src "ls180.v:8360.3-8362.6" - switch $not$ls180.v:8360$2781_Y + switch $not$ls180.v:8360$2783_Y attribute \src "ls180.v:8360.7-8360.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2782_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2784_Y case end attribute \src "ls180.v:8363.6-8363.10" @@ -299420,7 +299446,7 @@ module \ls180 switch \main_uart_rx_fifo_do_read attribute \src "ls180.v:8364.7-8364.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2783_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2785_Y case end end @@ -299470,7 +299496,7 @@ module \ls180 switch \main_spimaster32_clk_fall attribute \src "ls180.v:8396.7-8396.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2788_Y + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2790_Y attribute \src "ls180.v:8397.4-8399.7" switch \main_spimaster26_cs_enable attribute \src "ls180.v:8397.8-8397.34" @@ -299538,7 +299564,7 @@ module \ls180 switch \main_spisdcard_clk_fall attribute \src "ls180.v:8431.7-8431.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2793_Y + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2795_Y attribute \src "ls180.v:8432.4-8434.7" switch \main_spisdcard_cs_enable attribute \src "ls180.v:8432.8-8432.32" @@ -299582,9 +299608,9 @@ module \ls180 switch \main_pwm0_enable attribute \src "ls180.v:8452.6-8452.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2794_Y + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2796_Y attribute \src "ls180.v:8454.3-8458.6" - switch $lt$ls180.v:8454$2795_Y + switch $lt$ls180.v:8454$2797_Y attribute \src "ls180.v:8454.7-8454.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 @@ -299593,7 +299619,7 @@ module \ls180 assign $0\pwm[1:0] [0] 1'0 end attribute \src "ls180.v:8459.3-8461.6" - switch $ge$ls180.v:8459$2797_Y + switch $ge$ls180.v:8459$2799_Y attribute \src "ls180.v:8459.7-8459.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 @@ -299608,9 +299634,9 @@ module \ls180 switch \main_pwm1_enable attribute \src "ls180.v:8466.6-8466.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2798_Y + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2800_Y attribute \src "ls180.v:8468.3-8472.6" - switch $lt$ls180.v:8468$2799_Y + switch $lt$ls180.v:8468$2801_Y attribute \src "ls180.v:8468.7-8468.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 @@ -299619,7 +299645,7 @@ module \ls180 assign $0\pwm[1:0] [1] 1'0 end attribute \src "ls180.v:8473.3-8475.6" - switch $ge$ls180.v:8473$2801_Y + switch $ge$ls180.v:8473$2803_Y attribute \src "ls180.v:8473.7-8473.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 @@ -299631,10 +299657,10 @@ module \ls180 assign $0\pwm[1:0] [1] 1'0 end attribute \src "ls180.v:8480.2-8482.5" - switch $not$ls180.v:8480$2802_Y + switch $not$ls180.v:8480$2804_Y attribute \src "ls180.v:8480.6-8480.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2803_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2805_Y case end attribute \src "ls180.v:8486.2-8488.5" @@ -299655,7 +299681,7 @@ module \ls180 switch \main_sdphy_cmdr_cmdr_pads_in_valid attribute \src "ls180.v:8493.6-8493.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2804_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2806_Y case end attribute \src "ls180.v:8496.2-8498.5" @@ -299670,23 +299696,23 @@ module \ls180 attribute \src "ls180.v:8499.6-8499.46" case 1'1 attribute \src "ls180.v:8500.3-8505.6" - switch $or$ls180.v:8500$2806_Y + switch $or$ls180.v:8500$2808_Y attribute \src "ls180.v:8500.7-8500.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8503.7-8503.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2807_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2809_Y end case end attribute \src "ls180.v:8507.2-8520.5" - switch $and$ls180.v:8507$2808_Y + switch $and$ls180.v:8507$2810_Y attribute \src "ls180.v:8507.6-8507.97" case 1'1 attribute \src "ls180.v:8508.3-8514.6" - switch $and$ls180.v:8508$2809_Y + switch $and$ls180.v:8508$2811_Y attribute \src "ls180.v:8508.7-8508.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first @@ -299699,11 +299725,11 @@ module \ls180 attribute \src "ls180.v:8515.6-8515.10" case attribute \src "ls180.v:8516.3-8519.6" - switch $and$ls180.v:8516$2810_Y + switch $and$ls180.v:8516$2812_Y attribute \src "ls180.v:8516.7-8516.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2811_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2812_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2813_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2814_Y case end end @@ -299745,11 +299771,11 @@ module \ls180 switch \main_sdphy_cmdr_cmdr_converter_load_part attribute \src "ls180.v:8549.6-8549.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2813_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2815_Y case end attribute \src "ls180.v:8552.2-8557.5" - switch $or$ls180.v:8552$2815_Y + switch $or$ls180.v:8552$2817_Y attribute \src "ls180.v:8552.6-8552.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid @@ -299793,7 +299819,7 @@ module \ls180 switch \main_sdphy_dataw_crcr_pads_in_valid attribute \src "ls180.v:8574.6-8574.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2816_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2818_Y case end attribute \src "ls180.v:8577.2-8579.5" @@ -299808,23 +299834,23 @@ module \ls180 attribute \src "ls180.v:8580.6-8580.47" case 1'1 attribute \src "ls180.v:8581.3-8586.6" - switch $or$ls180.v:8581$2818_Y + switch $or$ls180.v:8581$2820_Y attribute \src "ls180.v:8581.7-8581.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8584.7-8584.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2819_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2821_Y end case end attribute \src "ls180.v:8588.2-8601.5" - switch $and$ls180.v:8588$2820_Y + switch $and$ls180.v:8588$2822_Y attribute \src "ls180.v:8588.6-8588.99" case 1'1 attribute \src "ls180.v:8589.3-8595.6" - switch $and$ls180.v:8589$2821_Y + switch $and$ls180.v:8589$2823_Y attribute \src "ls180.v:8589.7-8589.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first @@ -299837,11 +299863,11 @@ module \ls180 attribute \src "ls180.v:8596.6-8596.10" case attribute \src "ls180.v:8597.3-8600.6" - switch $and$ls180.v:8597$2822_Y + switch $and$ls180.v:8597$2824_Y attribute \src "ls180.v:8597.7-8597.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2823_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2824_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2825_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2826_Y case end end @@ -299883,11 +299909,11 @@ module \ls180 switch \main_sdphy_dataw_crcr_converter_load_part attribute \src "ls180.v:8630.6-8630.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2825_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2827_Y case end attribute \src "ls180.v:8633.2-8638.5" - switch $or$ls180.v:8633$2827_Y + switch $or$ls180.v:8633$2829_Y attribute \src "ls180.v:8633.6-8633.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid @@ -299924,7 +299950,7 @@ module \ls180 switch \main_sdphy_datar_datar_pads_in_valid attribute \src "ls180.v:8653.6-8653.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2828_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2830_Y case end attribute \src "ls180.v:8656.2-8658.5" @@ -299939,23 +299965,23 @@ module \ls180 attribute \src "ls180.v:8659.6-8659.48" case 1'1 attribute \src "ls180.v:8660.3-8665.6" - switch $or$ls180.v:8660$2830_Y + switch $or$ls180.v:8660$2832_Y attribute \src "ls180.v:8660.7-8660.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8663.7-8663.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2831_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2833_Y end case end attribute \src "ls180.v:8667.2-8680.5" - switch $and$ls180.v:8667$2832_Y + switch $and$ls180.v:8667$2834_Y attribute \src "ls180.v:8667.6-8667.101" case 1'1 attribute \src "ls180.v:8668.3-8674.6" - switch $and$ls180.v:8668$2833_Y + switch $and$ls180.v:8668$2835_Y attribute \src "ls180.v:8668.7-8668.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first @@ -299968,11 +299994,11 @@ module \ls180 attribute \src "ls180.v:8675.6-8675.10" case attribute \src "ls180.v:8676.3-8679.6" - switch $and$ls180.v:8676$2834_Y + switch $and$ls180.v:8676$2836_Y attribute \src "ls180.v:8676.7-8676.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2835_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2836_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2837_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2838_Y case end end @@ -299996,11 +300022,11 @@ module \ls180 switch \main_sdphy_datar_datar_converter_load_part attribute \src "ls180.v:8691.6-8691.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2837_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2839_Y case end attribute \src "ls180.v:8694.2-8699.5" - switch $or$ls180.v:8694$2839_Y + switch $or$ls180.v:8694$2841_Y attribute \src "ls180.v:8694.6-8694.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid @@ -300151,35 +300177,35 @@ module \ls180 case end attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2840_Y + switch $and$ls180.v:8767$2842_Y attribute \src "ls180.v:8767.6-8767.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2841_Y + switch $and$ls180.v:8770$2843_Y attribute \src "ls180.v:8770.6-8770.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2842_Y + switch $and$ls180.v:8773$2844_Y attribute \src "ls180.v:8773.6-8773.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end attribute \src "ls180.v:8776.2-8778.5" - switch $and$ls180.v:8776$2843_Y + switch $and$ls180.v:8776$2845_Y attribute \src "ls180.v:8776.6-8776.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end attribute \src "ls180.v:8779.2-8783.5" - switch $and$ls180.v:8779$2844_Y + switch $and$ls180.v:8779$2846_Y attribute \src "ls180.v:8779.6-8779.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } @@ -300188,7 +300214,7 @@ module \ls180 case end attribute \src "ls180.v:8784.2-8788.5" - switch $and$ls180.v:8784$2845_Y + switch $and$ls180.v:8784$2847_Y attribute \src "ls180.v:8784.6-8784.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } @@ -300197,7 +300223,7 @@ module \ls180 case end attribute \src "ls180.v:8789.2-8793.5" - switch $and$ls180.v:8789$2846_Y + switch $and$ls180.v:8789$2848_Y attribute \src "ls180.v:8789.6-8789.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } @@ -300206,7 +300232,7 @@ module \ls180 case end attribute \src "ls180.v:8794.2-8798.5" - switch $and$ls180.v:8794$2847_Y + switch $and$ls180.v:8794$2849_Y attribute \src "ls180.v:8794.6-8794.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } @@ -300215,7 +300241,7 @@ module \ls180 case end attribute \src "ls180.v:8799.2-8807.5" - switch $and$ls180.v:8799$2848_Y + switch $and$ls180.v:8799$2850_Y attribute \src "ls180.v:8799.6-8799.83" case 1'1 attribute \src "ls180.v:8800.3-8806.6" @@ -300226,10 +300252,10 @@ module \ls180 attribute \src "ls180.v:8802.7-8802.11" case attribute \src "ls180.v:8803.4-8805.7" - switch $ne$ls180.v:8803$2849_Y + switch $ne$ls180.v:8803$2851_Y attribute \src "ls180.v:8803.8-8803.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2850_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2852_Y case end end @@ -300359,28 +300385,28 @@ module \ls180 case end attribute \src "ls180.v:8864.2-8866.5" - switch $and$ls180.v:8864$2853_Y + switch $and$ls180.v:8864$2855_Y attribute \src "ls180.v:8864.6-8864.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2854_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2856_Y case end attribute \src "ls180.v:8867.2-8869.5" switch \main_sdblock2mem_fifo_do_read attribute \src "ls180.v:8867.6-8867.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2855_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2857_Y case end attribute \src "ls180.v:8870.2-8878.5" - switch $and$ls180.v:8870$2858_Y + switch $and$ls180.v:8870$2860_Y attribute \src "ls180.v:8870.6-8870.120" case 1'1 attribute \src "ls180.v:8871.3-8873.6" - switch $not$ls180.v:8871$2859_Y + switch $not$ls180.v:8871$2861_Y attribute \src "ls180.v:8871.7-8871.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2860_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2862_Y case end attribute \src "ls180.v:8874.6-8874.10" @@ -300389,7 +300415,7 @@ module \ls180 switch \main_sdblock2mem_fifo_do_read attribute \src "ls180.v:8875.7-8875.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2861_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2863_Y case end end @@ -300405,23 +300431,23 @@ module \ls180 attribute \src "ls180.v:8882.6-8882.42" case 1'1 attribute \src "ls180.v:8883.3-8888.6" - switch $or$ls180.v:8883$2863_Y + switch $or$ls180.v:8883$2865_Y attribute \src "ls180.v:8883.7-8883.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8886.7-8886.11" case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2864_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2866_Y end case end attribute \src "ls180.v:8890.2-8903.5" - switch $and$ls180.v:8890$2865_Y + switch $and$ls180.v:8890$2867_Y attribute \src "ls180.v:8890.6-8890.89" case 1'1 attribute \src "ls180.v:8891.3-8897.6" - switch $and$ls180.v:8891$2866_Y + switch $and$ls180.v:8891$2868_Y attribute \src "ls180.v:8891.7-8891.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first @@ -300434,11 +300460,11 @@ module \ls180 attribute \src "ls180.v:8898.6-8898.10" case attribute \src "ls180.v:8899.3-8902.6" - switch $and$ls180.v:8899$2867_Y + switch $and$ls180.v:8899$2869_Y attribute \src "ls180.v:8899.7-8899.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2868_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2869_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2870_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2871_Y case end end @@ -300480,7 +300506,7 @@ module \ls180 switch \main_sdblock2mem_converter_load_part attribute \src "ls180.v:8932.6-8932.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2870_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2872_Y case end attribute \src "ls180.v:8936.2-8938.5" @@ -300521,7 +300547,7 @@ module \ls180 case end attribute \src "ls180.v:8955.2-8961.5" - switch $and$ls180.v:8955$2871_Y + switch $and$ls180.v:8955$2873_Y attribute \src "ls180.v:8955.6-8955.89" case 1'1 attribute \src "ls180.v:8956.3-8960.6" @@ -300531,33 +300557,33 @@ module \ls180 assign $0\main_sdmem2block_converter_mux[2:0] 3'000 attribute \src "ls180.v:8958.7-8958.11" case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2872_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2874_Y end case end attribute \src "ls180.v:8962.2-8964.5" - switch $and$ls180.v:8962$2875_Y + switch $and$ls180.v:8962$2877_Y attribute \src "ls180.v:8962.6-8962.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2876_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2878_Y case end attribute \src "ls180.v:8965.2-8967.5" switch \main_sdmem2block_fifo_do_read attribute \src "ls180.v:8965.6-8965.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2877_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2879_Y case end attribute \src "ls180.v:8968.2-8976.5" - switch $and$ls180.v:8968$2880_Y + switch $and$ls180.v:8968$2882_Y attribute \src "ls180.v:8968.6-8968.120" case 1'1 attribute \src "ls180.v:8969.3-8971.6" - switch $not$ls180.v:8969$2881_Y + switch $not$ls180.v:8969$2883_Y attribute \src "ls180.v:8969.7-8969.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2882_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2884_Y case end attribute \src "ls180.v:8972.6-8972.10" @@ -300566,7 +300592,7 @@ module \ls180 switch \main_sdmem2block_fifo_do_read attribute \src "ls180.v:8973.7-8973.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2883_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2885_Y case end end @@ -300596,7 +300622,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'000 attribute \src "ls180.v:8989.4-9005.7" - switch $not$ls180.v:8989$2884_Y + switch $not$ls180.v:8989$2886_Y attribute \src "ls180.v:8989.8-8989.29" case 1'1 attribute \src "ls180.v:8990.5-9004.8" @@ -300635,7 +300661,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'001 attribute \src "ls180.v:9008.4-9024.7" - switch $not$ls180.v:9008$2885_Y + switch $not$ls180.v:9008$2887_Y attribute \src "ls180.v:9008.8-9008.29" case 1'1 attribute \src "ls180.v:9009.5-9023.8" @@ -300674,7 +300700,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 attribute \src "ls180.v:9027.4-9043.7" - switch $not$ls180.v:9027$2886_Y + switch $not$ls180.v:9027$2888_Y attribute \src "ls180.v:9027.8-9027.29" case 1'1 attribute \src "ls180.v:9028.5-9042.8" @@ -300713,7 +300739,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:9046.4-9062.7" - switch $not$ls180.v:9046$2887_Y + switch $not$ls180.v:9046$2889_Y attribute \src "ls180.v:9046.8-9046.29" case 1'1 attribute \src "ls180.v:9047.5-9061.8" @@ -300752,7 +300778,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 attribute \src "ls180.v:9065.4-9081.7" - switch $not$ls180.v:9065$2888_Y + switch $not$ls180.v:9065$2890_Y attribute \src "ls180.v:9065.8-9065.29" case 1'1 attribute \src "ls180.v:9066.5-9080.8" @@ -300795,10 +300821,10 @@ module \ls180 attribute \src "ls180.v:9085.6-9085.18" case 1'1 attribute \src "ls180.v:9086.3-9088.6" - switch $not$ls180.v:9086$2889_Y + switch $not$ls180.v:9086$2891_Y attribute \src "ls180.v:9086.7-9086.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9087$2890_Y + assign $0\builder_count[19:0] $sub$ls180.v:9087$2892_Y case end attribute \src "ls180.v:9089.6-9089.10" @@ -302196,14 +302222,14 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 assign $0\pwm[1:0] 2'00 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -302491,14 +302517,14 @@ module \ls180 case end sync posedge \sys_clk_1 - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] update \pwm $0\pwm[1:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] @@ -302909,7 +302935,7 @@ module \ls180 update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end attribute \src "ls180.v:784.11-784.68" - process $proc$ls180.v:784$3379 + process $proc$ls180.v:784$3381 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -302917,7 +302943,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:785.5-785.64" - process $proc$ls180.v:785$3380 + process $proc$ls180.v:785$3382 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -302925,7 +302951,7 @@ module \ls180 sync init end attribute \src "ls180.v:786.11-786.70" - process $proc$ls180.v:786$3381 + process $proc$ls180.v:786$3383 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -302933,7 +302959,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:787.11-787.70" - process $proc$ls180.v:787$3382 + process $proc$ls180.v:787$3384 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -302941,7 +302967,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:788.11-788.73" - process $proc$ls180.v:788$3383 + process $proc$ls180.v:788$3385 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -302949,7 +302975,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:809.5-809.59" - process $proc$ls180.v:809$3384 + process $proc$ls180.v:809$3386 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -302957,7 +302983,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:811.5-811.59" - process $proc$ls180.v:811$3385 + process $proc$ls180.v:811$3387 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always @@ -302965,7 +302991,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:812.5-812.58" - process $proc$ls180.v:812$3386 + process $proc$ls180.v:812$3388 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always @@ -302973,7 +302999,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:813.5-813.64" - process $proc$ls180.v:813$3387 + process $proc$ls180.v:813$3389 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -302981,7 +303007,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:814.12-814.74" - process $proc$ls180.v:814$3388 + process $proc$ls180.v:814$3390 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -302989,7 +303015,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:815.12-815.47" - process $proc$ls180.v:815$3389 + process $proc$ls180.v:815$3391 assign { } { } assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always @@ -302997,7 +303023,7 @@ module \ls180 update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end attribute \src "ls180.v:816.5-816.46" - process $proc$ls180.v:816$3390 + process $proc$ls180.v:816$3392 assign { } { } assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always @@ -303005,7 +303031,7 @@ module \ls180 update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end attribute \src "ls180.v:818.5-818.44" - process $proc$ls180.v:818$3391 + process $proc$ls180.v:818$3393 assign { } { } assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always @@ -303013,7 +303039,7 @@ module \ls180 update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end attribute \src "ls180.v:819.5-819.45" - process $proc$ls180.v:819$3392 + process $proc$ls180.v:819$3394 assign { } { } assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 sync always @@ -303021,7 +303047,7 @@ module \ls180 update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end attribute \src "ls180.v:820.5-820.54" - process $proc$ls180.v:820$3393 + process $proc$ls180.v:820$3395 assign { } { } assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always @@ -303029,7 +303055,7 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:822.32-822.76" - process $proc$ls180.v:822$3394 + process $proc$ls180.v:822$3396 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always @@ -303037,7 +303063,7 @@ module \ls180 update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end attribute \src "ls180.v:823.11-823.55" - process $proc$ls180.v:823$3395 + process $proc$ls180.v:823$3397 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always @@ -303045,7 +303071,7 @@ module \ls180 update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end attribute \src "ls180.v:825.32-825.75" - process $proc$ls180.v:825$3396 + process $proc$ls180.v:825$3398 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always @@ -303053,7 +303079,7 @@ module \ls180 sync init end attribute \src "ls180.v:827.32-827.76" - process $proc$ls180.v:827$3397 + process $proc$ls180.v:827$3399 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always @@ -303061,7 +303087,7 @@ module \ls180 sync init end attribute \src "ls180.v:830.5-830.44" - process $proc$ls180.v:830$3398 + process $proc$ls180.v:830$3400 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always @@ -303069,7 +303095,7 @@ module \ls180 sync init end attribute \src "ls180.v:831.5-831.45" - process $proc$ls180.v:831$3399 + process $proc$ls180.v:831$3401 assign { } { } assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always @@ -303077,7 +303103,7 @@ module \ls180 sync init end attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3400 + process $proc$ls180.v:832$3402 assign { } { } assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always @@ -303085,7 +303111,7 @@ module \ls180 sync init end attribute \src "ls180.v:833.5-833.48" - process $proc$ls180.v:833$3401 + process $proc$ls180.v:833$3403 assign { } { } assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always @@ -303093,7 +303119,7 @@ module \ls180 sync init end attribute \src "ls180.v:835.5-835.43" - process $proc$ls180.v:835$3402 + process $proc$ls180.v:835$3404 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always @@ -303101,7 +303127,7 @@ module \ls180 sync init end attribute \src "ls180.v:838.5-838.49" - process $proc$ls180.v:838$3403 + process $proc$ls180.v:838$3405 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always @@ -303109,7 +303135,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end attribute \src "ls180.v:839.5-839.49" - process $proc$ls180.v:839$3404 + process $proc$ls180.v:839$3406 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always @@ -303117,7 +303143,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:840.5-840.48" - process $proc$ls180.v:840$3405 + process $proc$ls180.v:840$3407 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always @@ -303125,7 +303151,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end attribute \src "ls180.v:844.11-844.46" - process $proc$ls180.v:844$3406 + process $proc$ls180.v:844$3408 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always @@ -303133,7 +303159,7 @@ module \ls180 update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:846.11-846.45" - process $proc$ls180.v:846$3407 + process $proc$ls180.v:846$3409 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always @@ -303141,7 +303167,7 @@ module \ls180 update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end attribute \src "ls180.v:848.5-848.44" - process $proc$ls180.v:848$3408 + process $proc$ls180.v:848$3410 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always @@ -303149,7 +303175,7 @@ module \ls180 update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end attribute \src "ls180.v:849.5-849.45" - process $proc$ls180.v:849$3409 + process $proc$ls180.v:849$3411 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always @@ -303157,7 +303183,7 @@ module \ls180 update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$3134 + process $proc$ls180.v:85$3136 assign { } { } assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 sync always @@ -303165,7 +303191,7 @@ module \ls180 sync init end attribute \src "ls180.v:851.5-851.48" - process $proc$ls180.v:851$3410 + process $proc$ls180.v:851$3412 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always @@ -303173,7 +303199,7 @@ module \ls180 update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end attribute \src "ls180.v:853.5-853.43" - process $proc$ls180.v:853$3411 + process $proc$ls180.v:853$3413 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always @@ -303181,7 +303207,7 @@ module \ls180 update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end attribute \src "ls180.v:856.5-856.49" - process $proc$ls180.v:856$3412 + process $proc$ls180.v:856$3414 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always @@ -303189,7 +303215,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end attribute \src "ls180.v:857.5-857.49" - process $proc$ls180.v:857$3413 + process $proc$ls180.v:857$3415 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always @@ -303197,7 +303223,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:858.5-858.48" - process $proc$ls180.v:858$3414 + process $proc$ls180.v:858$3416 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always @@ -303205,7 +303231,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$3135 + process $proc$ls180.v:86$3137 assign { } { } assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 sync always @@ -303213,7 +303239,7 @@ module \ls180 sync init end attribute \src "ls180.v:862.11-862.46" - process $proc$ls180.v:862$3415 + process $proc$ls180.v:862$3417 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always @@ -303221,7 +303247,7 @@ module \ls180 update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end attribute \src "ls180.v:864.11-864.45" - process $proc$ls180.v:864$3416 + process $proc$ls180.v:864$3418 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always @@ -303229,7 +303255,7 @@ module \ls180 update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end attribute \src "ls180.v:866.12-866.36" - process $proc$ls180.v:866$3417 + process $proc$ls180.v:866$3419 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always @@ -303237,7 +303263,7 @@ module \ls180 sync init end attribute \src "ls180.v:867.11-867.35" - process $proc$ls180.v:867$3418 + process $proc$ls180.v:867$3420 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always @@ -303245,7 +303271,7 @@ module \ls180 sync init end attribute \src "ls180.v:868.11-868.40" - process $proc$ls180.v:868$3419 + process $proc$ls180.v:868$3421 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always @@ -303253,7 +303279,7 @@ module \ls180 update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end attribute \src "ls180.v:869.5-869.31" - process $proc$ls180.v:869$3420 + process $proc$ls180.v:869$3422 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always @@ -303261,7 +303287,7 @@ module \ls180 sync init end attribute \src "ls180.v:870.5-870.31" - process $proc$ls180.v:870$3421 + process $proc$ls180.v:870$3423 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always @@ -303269,7 +303295,7 @@ module \ls180 sync init end attribute \src "ls180.v:872.32-872.63" - process $proc$ls180.v:872$3422 + process $proc$ls180.v:872$3424 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always @@ -303277,7 +303303,7 @@ module \ls180 sync init end attribute \src "ls180.v:874.32-874.63" - process $proc$ls180.v:874$3423 + process $proc$ls180.v:874$3425 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always @@ -303285,7 +303311,7 @@ module \ls180 sync init end attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3424 + process $proc$ls180.v:876$3426 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always @@ -303293,7 +303319,7 @@ module \ls180 update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end attribute \src "ls180.v:877.5-877.36" - process $proc$ls180.v:877$3425 + process $proc$ls180.v:877$3427 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always @@ -303301,7 +303327,7 @@ module \ls180 update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end attribute \src "ls180.v:879.32-879.63" - process $proc$ls180.v:879$3426 + process $proc$ls180.v:879$3428 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always @@ -303309,7 +303335,7 @@ module \ls180 update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$3136 + process $proc$ls180.v:88$3138 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303317,7 +303343,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end attribute \src "ls180.v:880.11-880.42" - process $proc$ls180.v:880$3427 + process $proc$ls180.v:880$3429 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always @@ -303325,7 +303351,7 @@ module \ls180 update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3428 + process $proc$ls180.v:883$3430 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always @@ -303333,7 +303359,7 @@ module \ls180 update \main_sdram_en0 $1\main_sdram_en0[0:0] end attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3429 + process $proc$ls180.v:885$3431 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always @@ -303341,7 +303367,7 @@ module \ls180 update \main_sdram_time0 $1\main_sdram_time0[4:0] end attribute \src "ls180.v:886.5-886.26" - process $proc$ls180.v:886$3430 + process $proc$ls180.v:886$3432 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always @@ -303349,7 +303375,7 @@ module \ls180 update \main_sdram_en1 $1\main_sdram_en1[0:0] end attribute \src "ls180.v:888.11-888.34" - process $proc$ls180.v:888$3431 + process $proc$ls180.v:888$3433 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always @@ -303357,7 +303383,7 @@ module \ls180 update \main_sdram_time1 $1\main_sdram_time1[3:0] end attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$3137 + process $proc$ls180.v:89$3139 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 sync always @@ -303365,7 +303391,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end attribute \src "ls180.v:903.12-903.37" - process $proc$ls180.v:903$3432 + process $proc$ls180.v:903$3434 assign { } { } assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303373,7 +303399,7 @@ module \ls180 update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end attribute \src "ls180.v:904.12-904.39" - process $proc$ls180.v:904$3433 + process $proc$ls180.v:904$3435 assign { } { } assign $1\main_wb_sdram_dat_w[31:0] 0 sync always @@ -303381,7 +303407,7 @@ module \ls180 update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end attribute \src "ls180.v:906.11-906.35" - process $proc$ls180.v:906$3434 + process $proc$ls180.v:906$3436 assign { } { } assign $1\main_wb_sdram_sel[3:0] 4'0000 sync always @@ -303389,7 +303415,7 @@ module \ls180 update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] end attribute \src "ls180.v:907.5-907.29" - process $proc$ls180.v:907$3435 + process $proc$ls180.v:907$3437 assign { } { } assign $1\main_wb_sdram_cyc[0:0] 1'0 sync always @@ -303397,7 +303423,7 @@ module \ls180 update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] end attribute \src "ls180.v:908.5-908.29" - process $proc$ls180.v:908$3436 + process $proc$ls180.v:908$3438 assign { } { } assign $1\main_wb_sdram_stb[0:0] 1'0 sync always @@ -303405,7 +303431,7 @@ module \ls180 update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] end attribute \src "ls180.v:909.5-909.29" - process $proc$ls180.v:909$3437 + process $proc$ls180.v:909$3439 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always @@ -303413,7 +303439,7 @@ module \ls180 update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$3138 + process $proc$ls180.v:91$3140 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 sync always @@ -303421,7 +303447,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] end attribute \src "ls180.v:910.5-910.28" - process $proc$ls180.v:910$3438 + process $proc$ls180.v:910$3440 assign { } { } assign $1\main_wb_sdram_we[0:0] 1'0 sync always @@ -303429,7 +303455,7 @@ module \ls180 update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] end attribute \src "ls180.v:917.5-917.54" - process $proc$ls180.v:917$3439 + process $proc$ls180.v:917$3441 assign { } { } assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 sync always @@ -303437,7 +303463,7 @@ module \ls180 update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] end attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3139 + process $proc$ls180.v:92$3141 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 sync always @@ -303445,7 +303471,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] end attribute \src "ls180.v:921.5-921.54" - process $proc$ls180.v:921$3440 + process $proc$ls180.v:921$3442 assign { } { } assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 sync always @@ -303453,7 +303479,7 @@ module \ls180 sync init end attribute \src "ls180.v:922.5-922.35" - process $proc$ls180.v:922$3441 + process $proc$ls180.v:922$3443 assign { } { } assign $1\main_socbushandler_skip[0:0] 1'0 sync always @@ -303461,7 +303487,7 @@ module \ls180 update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end attribute \src "ls180.v:923.5-923.38" - process $proc$ls180.v:923$3442 + process $proc$ls180.v:923$3444 assign { } { } assign $1\main_socbushandler_counter[0:0] 1'0 sync always @@ -303469,7 +303495,7 @@ module \ls180 update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] end attribute \src "ls180.v:925.12-925.44" - process $proc$ls180.v:925$3443 + process $proc$ls180.v:925$3445 assign { } { } assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -303477,7 +303503,7 @@ module \ls180 update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end attribute \src "ls180.v:926.12-926.40" - process $proc$ls180.v:926$3444 + process $proc$ls180.v:926$3446 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303485,7 +303511,7 @@ module \ls180 update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end attribute \src "ls180.v:927.12-927.42" - process $proc$ls180.v:927$3445 + process $proc$ls180.v:927$3447 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always @@ -303493,7 +303519,7 @@ module \ls180 update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end attribute \src "ls180.v:929.11-929.38" - process $proc$ls180.v:929$3446 + process $proc$ls180.v:929$3448 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always @@ -303501,7 +303527,7 @@ module \ls180 update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3140 + process $proc$ls180.v:93$3142 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 sync always @@ -303509,7 +303535,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] end attribute \src "ls180.v:930.5-930.32" - process $proc$ls180.v:930$3447 + process $proc$ls180.v:930$3449 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always @@ -303517,7 +303543,7 @@ module \ls180 update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end attribute \src "ls180.v:931.5-931.32" - process $proc$ls180.v:931$3448 + process $proc$ls180.v:931$3450 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always @@ -303525,7 +303551,7 @@ module \ls180 update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end attribute \src "ls180.v:933.5-933.31" - process $proc$ls180.v:933$3449 + process $proc$ls180.v:933$3451 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always @@ -303533,7 +303559,7 @@ module \ls180 update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end attribute \src "ls180.v:934.5-934.31" - process $proc$ls180.v:934$3450 + process $proc$ls180.v:934$3452 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always @@ -303541,7 +303567,7 @@ module \ls180 update \main_converter_skip $1\main_converter_skip[0:0] end attribute \src "ls180.v:935.5-935.34" - process $proc$ls180.v:935$3451 + process $proc$ls180.v:935$3453 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always @@ -303549,7 +303575,7 @@ module \ls180 update \main_converter_counter $1\main_converter_counter[0:0] end attribute \src "ls180.v:937.12-937.40" - process $proc$ls180.v:937$3452 + process $proc$ls180.v:937$3454 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always @@ -303557,7 +303583,7 @@ module \ls180 update \main_converter_dat_r $1\main_converter_dat_r[31:0] end attribute \src "ls180.v:938.5-938.29" - process $proc$ls180.v:938$3453 + process $proc$ls180.v:938$3455 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always @@ -303565,7 +303591,7 @@ module \ls180 update \main_cmd_consumed $1\main_cmd_consumed[0:0] end attribute \src "ls180.v:939.5-939.31" - process $proc$ls180.v:939$3454 + process $proc$ls180.v:939$3456 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always @@ -303573,7 +303599,7 @@ module \ls180 update \main_wdata_consumed $1\main_wdata_consumed[0:0] end attribute \src "ls180.v:943.12-943.47" - process $proc$ls180.v:943$3455 + process $proc$ls180.v:943$3457 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always @@ -303581,7 +303607,7 @@ module \ls180 update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end attribute \src "ls180.v:944.5-944.28" - process $proc$ls180.v:944$3456 + process $proc$ls180.v:944$3458 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always @@ -303589,7 +303615,7 @@ module \ls180 update \main_uart_phy_re $1\main_uart_phy_re[0:0] end attribute \src "ls180.v:946.5-946.36" - process $proc$ls180.v:946$3457 + process $proc$ls180.v:946$3459 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always @@ -303597,7 +303623,7 @@ module \ls180 update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3141 + process $proc$ls180.v:95$3143 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 sync always @@ -303605,7 +303631,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] end attribute \src "ls180.v:950.5-950.39" - process $proc$ls180.v:950$3458 + process $proc$ls180.v:950$3460 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always @@ -303613,7 +303639,7 @@ module \ls180 update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end attribute \src "ls180.v:951.12-951.54" - process $proc$ls180.v:951$3459 + process $proc$ls180.v:951$3461 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always @@ -303621,7 +303647,7 @@ module \ls180 update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end attribute \src "ls180.v:952.11-952.38" - process $proc$ls180.v:952$3460 + process $proc$ls180.v:952$3462 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always @@ -303629,7 +303655,7 @@ module \ls180 update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end attribute \src "ls180.v:953.11-953.43" - process $proc$ls180.v:953$3461 + process $proc$ls180.v:953$3463 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always @@ -303637,7 +303663,7 @@ module \ls180 update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end attribute \src "ls180.v:954.5-954.33" - process $proc$ls180.v:954$3462 + process $proc$ls180.v:954$3464 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always @@ -303645,7 +303671,7 @@ module \ls180 update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end attribute \src "ls180.v:955.5-955.38" - process $proc$ls180.v:955$3463 + process $proc$ls180.v:955$3465 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always @@ -303653,7 +303679,7 @@ module \ls180 update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end attribute \src "ls180.v:957.5-957.38" - process $proc$ls180.v:957$3464 + process $proc$ls180.v:957$3466 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always @@ -303661,7 +303687,7 @@ module \ls180 sync init end attribute \src "ls180.v:958.5-958.37" - process $proc$ls180.v:958$3465 + process $proc$ls180.v:958$3467 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always @@ -303669,7 +303695,7 @@ module \ls180 sync init end attribute \src "ls180.v:959.11-959.51" - process $proc$ls180.v:959$3466 + process $proc$ls180.v:959$3468 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always @@ -303677,7 +303703,7 @@ module \ls180 update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end attribute \src "ls180.v:960.5-960.39" - process $proc$ls180.v:960$3467 + process $proc$ls180.v:960$3469 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always @@ -303685,7 +303711,7 @@ module \ls180 update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end attribute \src "ls180.v:961.12-961.54" - process $proc$ls180.v:961$3468 + process $proc$ls180.v:961$3470 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always @@ -303693,7 +303719,7 @@ module \ls180 update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end attribute \src "ls180.v:963.5-963.30" - process $proc$ls180.v:963$3469 + process $proc$ls180.v:963$3471 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always @@ -303701,7 +303727,7 @@ module \ls180 update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end attribute \src "ls180.v:964.11-964.38" - process $proc$ls180.v:964$3470 + process $proc$ls180.v:964$3472 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always @@ -303709,7 +303735,7 @@ module \ls180 update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end attribute \src "ls180.v:965.11-965.43" - process $proc$ls180.v:965$3471 + process $proc$ls180.v:965$3473 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always @@ -303717,7 +303743,7 @@ module \ls180 update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end attribute \src "ls180.v:966.5-966.33" - process $proc$ls180.v:966$3472 + process $proc$ls180.v:966$3474 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always @@ -303725,7 +303751,7 @@ module \ls180 update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$3142 + process $proc$ls180.v:97$3144 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303733,7 +303759,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] end attribute \src "ls180.v:977.5-977.32" - process $proc$ls180.v:977$3473 + process $proc$ls180.v:977$3475 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always @@ -303741,7 +303767,7 @@ module \ls180 update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end attribute \src "ls180.v:979.5-979.30" - process $proc$ls180.v:979$3474 + process $proc$ls180.v:979$3476 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always @@ -303749,7 +303775,7 @@ module \ls180 update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3143 + process $proc$ls180.v:98$3145 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 sync always @@ -303757,7 +303783,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end attribute \src "ls180.v:980.5-980.36" - process $proc$ls180.v:980$3475 + process $proc$ls180.v:980$3477 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always @@ -303765,7 +303791,7 @@ module \ls180 update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end attribute \src "ls180.v:982.5-982.32" - process $proc$ls180.v:982$3476 + process $proc$ls180.v:982$3478 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always @@ -303773,7 +303799,7 @@ module \ls180 update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end attribute \src "ls180.v:984.5-984.30" - process $proc$ls180.v:984$3477 + process $proc$ls180.v:984$3479 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always @@ -303781,7 +303807,7 @@ module \ls180 update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end attribute \src "ls180.v:985.5-985.36" - process $proc$ls180.v:985$3478 + process $proc$ls180.v:985$3480 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always @@ -303789,7 +303815,7 @@ module \ls180 update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end attribute \src "ls180.v:989.11-989.49" - process $proc$ls180.v:989$3479 + process $proc$ls180.v:989$3481 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always @@ -303797,7 +303823,7 @@ module \ls180 update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end attribute \src "ls180.v:993.11-993.50" - process $proc$ls180.v:993$3480 + process $proc$ls180.v:993$3482 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always @@ -303805,7 +303831,7 @@ module \ls180 update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end attribute \src "ls180.v:994.11-994.48" - process $proc$ls180.v:994$3481 + process $proc$ls180.v:994$3483 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always @@ -303813,7 +303839,7 @@ module \ls180 update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end attribute \src "ls180.v:995.5-995.37" - process $proc$ls180.v:995$3482 + process $proc$ls180.v:995$3484 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always @@ -305558,27 +305584,27 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2916_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2942_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2968_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2994_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3020_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2918_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2944_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2970_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2996_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3022_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3027_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3029_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3034_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3036_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3041_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3043_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3048_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3050_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3069_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3071_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3078_DATA end attribute \src "libresoc.v:146562.1-146620.10" attribute \cells_not_processed 1 -- 2.30.2