From c97af4854e66e450e94a4842ab71a25df5d402fc Mon Sep 17 00:00:00 2001 From: eavivi Date: Fri, 4 Sep 2020 13:23:33 -0700 Subject: [PATCH] learning-gem5: convert simple cache to new style stats Change-Id: I6988c45c13955825fde974f390460f4473af017a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34135 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/learning_gem5/part2/simple_cache.cc | 40 ++++++++----------------- src/learning_gem5/part2/simple_cache.hh | 17 ++++++----- 2 files changed, 21 insertions(+), 36 deletions(-) diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 25f6bd7bb..ad5e6631d 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -38,7 +38,7 @@ SimpleCache::SimpleCache(SimpleCacheParams *params) : blockSize(params->system->cacheLineSize()), capacity(params->size / blockSize), memPort(params->name + ".mem_side", this), - blocked(false), originalPacket(nullptr), waitingPortId(-1) + blocked(false), originalPacket(nullptr), waitingPortId(-1), stats(this) { // Since the CPU side ports are a vector of ports, create an instance of // the CPUSidePort for each connection. This member of params is @@ -221,7 +221,7 @@ SimpleCache::handleResponse(PacketPtr pkt) // for any added latency. insert(pkt); - missLatency.sample(curTick() - missTime); + stats.missLatency.sample(curTick() - missTime); // If we had to upgrade the request packet to a full cache line, now we // can use that packet to construct the response. @@ -286,12 +286,12 @@ SimpleCache::accessTiming(PacketPtr pkt) if (hit) { // Respond to the CPU side - hits++; // update stats + stats.hits++; // update stats DDUMP(SimpleCache, pkt->getConstPtr(), pkt->getSize()); pkt->makeResponse(); sendResponse(pkt); } else { - misses++; // update stats + stats.misses++; // update stats missTime = curTick(); // Forward to the memory side. // We can't directly forward the packet unless it is exactly the size @@ -421,31 +421,15 @@ SimpleCache::sendRangeChange() const } } -void -SimpleCache::regStats() +SimpleCache::SimpleCacheStats::SimpleCacheStats(Stats::Group *parent) + : Stats::Group(parent), + ADD_STAT(hits, "Number of hits"), + ADD_STAT(misses, "Number of misses"), + ADD_STAT(missLatency, "Ticks for misses to the cache"), + ADD_STAT(hitRatio, "The ratio of hits to the total" + "accesses to the cache", hits / (hits + misses)) { - // If you don't do this you get errors about uninitialized stats. - ClockedObject::regStats(); - - hits.name(name() + ".hits") - .desc("Number of hits") - ; - - misses.name(name() + ".misses") - .desc("Number of misses") - ; - - missLatency.name(name() + ".missLatency") - .desc("Ticks for misses to the cache") - .init(16) // number of buckets - ; - - hitRatio.name(name() + ".hitRatio") - .desc("The ratio of hits to the total accesses to the cache") - ; - - hitRatio = hits / (hits + misses); - + missLatency.init(16); // number of buckets } diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh index 4e57c87bd..6dae1e41a 100644 --- a/src/learning_gem5/part2/simple_cache.hh +++ b/src/learning_gem5/part2/simple_cache.hh @@ -292,10 +292,15 @@ class SimpleCache : public ClockedObject std::unordered_map cacheStore; /// Cache statistics - Stats::Scalar hits; - Stats::Scalar misses; - Stats::Histogram missLatency; - Stats::Formula hitRatio; + protected: + struct SimpleCacheStats : public Stats::Group + { + SimpleCacheStats(Stats::Group *parent); + Stats::Scalar hits; + Stats::Scalar misses; + Stats::Histogram missLatency; + Stats::Formula hitRatio; + } stats; public: @@ -316,10 +321,6 @@ class SimpleCache : public ClockedObject Port &getPort(const std::string &if_name, PortID idx=InvalidPortID) override; - /** - * Register the stats - */ - void regStats() override; }; -- 2.30.2