From c9b7dadc694d4aad59b5d7dcaa6fdd9187b76bdf Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 16 Jul 2020 20:07:18 -0700 Subject: [PATCH] rename DIV->Div to be consistent --- src/soc/fu/div/input_stage.py | 6 +++--- src/soc/fu/div/output_stage.py | 2 +- src/soc/fu/div/pipe_data.py | 8 ++++---- src/soc/fu/div/pipeline.py | 2 +- src/soc/fu/div/setup_stage.py | 6 +++--- src/soc/fu/div/test/test_pipe_caller.py | 20 ++++++++++---------- 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/soc/fu/div/input_stage.py b/src/soc/fu/div/input_stage.py index 01888cb2..08e4c132 100644 --- a/src/soc/fu/div/input_stage.py +++ b/src/soc/fu/div/input_stage.py @@ -3,7 +3,7 @@ # generation for subtraction, and handling of immediates should happen # in the base class (CommonInputStage.elaborate). from soc.fu.alu.input_stage import ALUInputStage -from soc.fu.div.pipe_data import DIVInputData +from soc.fu.div.pipe_data import DivInputData # simply over-ride ALUInputStage ispec / ospec @@ -12,5 +12,5 @@ class DivMulInputStage(ALUInputStage): def __init__(self, pspec): super().__init__(pspec) - def ispec(self): return DIVInputData(self.pspec) - def ospec(self): return DIVInputData(self.pspec) + def ispec(self): return DivInputData(self.pspec) + def ospec(self): return DivInputData(self.pspec) diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 7348538c..4970a807 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -109,7 +109,7 @@ class DivOutputStage(PipeModBase): comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32 ########################## - # main switch for DIV + # main switch for Div o = self.o.o.data diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index 80a408be..d8dd7393 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -7,7 +7,7 @@ from ieee754.div_rem_sqrt_rsqrt.core import ( DivPipeCoreInterstageData, DivPipeCoreOutputData) -class DIVInputData(IntegerData): +class DivInputData(IntegerData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('XER', 'xer_so', '32'), ] # XER bit 32: SO @@ -31,8 +31,8 @@ class DivMulOutputData(IntegerData): self.cr0 = self.cr_a -class DIVPipeSpec(CommonPipeSpec): - regspec = (DIVInputData.regspec, DivMulOutputData.regspec) +class DivPipeSpec(CommonPipeSpec): + regspec = (DivInputData.regspec, DivMulOutputData.regspec) opsubsetkls = CompLogicalOpSubset core_config = DivPipeCoreConfig( bit_width=64, @@ -42,7 +42,7 @@ class DIVPipeSpec(CommonPipeSpec): ) -class CoreBaseData(DIVInputData): +class CoreBaseData(DivInputData): def __init__(self, pspec, core_data_class): super().__init__(pspec) self.core = core_data_class(pspec.core_config) diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py index 3fa56350..05cece6b 100644 --- a/src/soc/fu/div/pipeline.py +++ b/src/soc/fu/div/pipeline.py @@ -38,7 +38,7 @@ class DivStagesEnd(PipeModBaseChain): return [core_final, div_out, alu_out] -class DIVBasePipe(ControlBase): +class DivBasePipe(ControlBase): def __init__(self, pspec, compute_steps_per_stage=4): ControlBase.__init__(self) self.pipe_start = DivStagesStart(pspec) diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py index 679c9cc6..8928f25c 100644 --- a/src/soc/fu/div/setup_stage.py +++ b/src/soc/fu/div/setup_stage.py @@ -3,7 +3,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase -from soc.fu.div.pipe_data import DIVInputData +from soc.fu.div.pipe_data import DivInputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import MicrOp @@ -21,7 +21,7 @@ class DivSetupStage(PipeModBase): self.fields.create_specs() def ispec(self): - return DIVInputData(self.pspec) + return DivInputData(self.pspec) def ospec(self): return CoreInputData(self.pspec) @@ -67,7 +67,7 @@ class DivSetupStage(PipeModBase): comb += self.o.div_by_zero.eq(divisor_o == 0) ########################## - # main switch for DIV + # main switch for Div with m.Switch(op.insn_type): # div/mod takes straight (absolute) dividend diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 35d21182..e0746aef 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -13,8 +13,8 @@ from soc.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.fu.test.common import (TestCase, ALUHelpers) -from soc.fu.div.pipeline import DIVBasePipe -from soc.fu.div.pipe_data import DIVPipeSpec +from soc.fu.div.pipeline import DivBasePipe +from soc.fu.div.pipe_data import DivPipeSpec import random @@ -24,7 +24,7 @@ def log_rand(n, min_val=1): def get_cu_inputs(dec2, sim): - """naming (res) must conform to DIVFunctionUnit input regspec + """naming (res) must conform to DivFunctionUnit input regspec """ res = {} @@ -56,7 +56,7 @@ def set_alu_inputs(alu, dec2, sim): # should have. However, this was really slow, since it needed to # create and tear down the dut and simulator for every test case. -# Now, instead of doing that, every test case in DIVTestCase puts some +# Now, instead of doing that, every test case in DivTestCase puts some # data into the test_data list below, describing the instructions to # be tested and the initial state. Once all the tests have been run, # test_data gets passed to TestRunner which then sets up the DUT and @@ -68,7 +68,7 @@ def set_alu_inputs(alu, dec2, sim): # takes around 3 seconds -class DIVTestCase(FHDLTestCase): +class DivTestCase(FHDLTestCase): test_data = [] def __init__(self, name): @@ -200,8 +200,8 @@ class DIVTestCase(FHDLTestCase): self.run_tst_program(Program(lst, bigendian), initial_regs) def tst_ilang(self): - pspec = DIVPipeSpec(id_wid=2) - alu = DIVBasePipe(pspec) + pspec = DivPipeSpec(id_wid=2) + alu = DivBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("div_pipeline.il", "w") as f: f.write(vl) @@ -221,8 +221,8 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = DIVPipeSpec(id_wid=2) - m.submodules.alu = alu = DIVBasePipe(pspec) + pspec = DivPipeSpec(id_wid=2) + m.submodules.alu = alu = DivBasePipe(pspec) comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) comb += alu.n.ready_i.eq(1) @@ -351,7 +351,7 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(DIVTestCase.test_data)) + suite.addTest(TestRunner(DivTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2