From c9c9307a5e6cf4ec514cb810ff2eff1273de1811 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 28 Mar 2019 17:50:14 +0000 Subject: [PATCH] test_sim: add missing add_process(). Fixes #43. --- nmigen/test/test_sim.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index 6a09a5b..ff3986d 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -376,9 +376,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase): with self.assertSimulation(Module(), deadline=100e-6) as sim: sim.add_clock(1e-6) def process(): - for _ in range(100): - yield + for _ in range(101): + yield Delay(1e-6) self.fail() + sim.add_process(process) def test_add_process_wrong(self): with self.assertSimulation(Module()) as sim: -- 2.30.2