From c9cd3d10a4484567336527ac4b7c04f8267b116a Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Fri, 14 Dec 2018 15:23:22 +0000
Subject: [PATCH] =?utf8?q?back.pysim:=20Simulator({gtkw=5Fsignals=E2=86=92?=
 =?utf8?q?traces}=3D).?=
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---
 examples/ctrl.py        | 2 +-
 nmigen/back/pysim.py    | 7 +++----
 nmigen/test/test_sim.py | 2 +-
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/examples/ctrl.py b/examples/ctrl.py
index b2d352d..64c3b5d 100644
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -24,7 +24,7 @@ print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
 with pysim.Simulator(frag,
         vcd_file=open("ctrl.vcd", "w"),
         gtkw_file=open("ctrl.gtkw", "w"),
-        gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
+        traces=[ctr.ce, ctr.v, ctr.o]) as sim:
     sim.add_clock(1e-6)
     def ce_proc():
         yield; yield; yield
diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 3b72d77..ba32dbf 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -191,7 +191,7 @@ class _StatementCompiler(StatementTransformer):
 
 
 class Simulator:
-    def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()):
+    def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
         self._fragment        = fragment
 
         self._domains         = {}            # str/domain -> ClockDomain
@@ -221,9 +221,8 @@ class Simulator:
         self._vcd_writer      = None
         self._vcd_signals     = ValueDict()   # signal -> set(vcd_signal)
         self._vcd_names       = ValueDict()   # signal -> str/name
-
         self._gtkw_file       = gtkw_file
-        self._gtkw_signals    = gtkw_signals
+        self._traces          = traces
 
     def _check_process(self, process):
         if inspect.isgeneratorfunction(process):
@@ -578,7 +577,7 @@ class Simulator:
                         add_trace(cd.rst)
                     add_trace(cd.clk)
 
-            for signal in self._gtkw_signals:
+            for signal in self._traces:
                 add_trace(signal)
 
         if self._vcd_file:
diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index c0bec55..4b29c75 100644
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -19,7 +19,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
         with Simulator(frag,
                 vcd_file =open("test.vcd",  "w"),
                 gtkw_file=open("test.gtkw", "w"),
-                gtkw_signals=[*isigs, osig]) as sim:
+                traces=[*isigs, osig]) as sim:
             def process():
                 for isig, input in zip(isigs, inputs):
                     yield isig.eq(input)
-- 
2.30.2