From c9dbe52f848ae795ae9fdd7cbeca857db27dcc48 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 17 Sep 2018 16:34:11 +0200 Subject: [PATCH] radv: implement VK_EXT_conservative_rasterization Only supported by GFX9+. The conservativeraster Sascha demo seems to work as expected. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 14 +++++++++ src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_pipeline.c | 49 ++++++++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 8b7e64e3023..f9169d9d012 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1179,6 +1179,20 @@ void radv_GetPhysicalDeviceProperties2( properties->protectedNoFault = false; break; } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: { + VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties = + (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext; + properties->primitiveOverestimationSize = 0; + properties->maxExtraPrimitiveOverestimationSize = 0; + properties->extraPrimitiveOverestimationSizeGranularity = 0; + properties->primitiveUnderestimation = VK_FALSE; + properties->conservativePointAndLineRasterization = VK_FALSE; + properties->degenerateTrianglesRasterized = VK_FALSE; + properties->degenerateLinesRasterized = VK_FALSE; + properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE; + properties->conservativeRasterizationPostDepthCoverage = VK_FALSE; + break; + } default: break; } diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py index fa35aabd3ba..584926df390 100644 --- a/src/amd/vulkan/radv_extensions.py +++ b/src/amd/vulkan/radv_extensions.py @@ -93,6 +93,7 @@ EXTENSIONS = [ Extension('VK_EXT_direct_mode_display', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_EXT_acquire_xlib_display', 1, 'VK_USE_PLATFORM_XLIB_XRANDR_EXT'), Extension('VK_EXT_conditional_rendering', 1, True), + Extension('VK_EXT_conservative_rasterization', 1, 'device->rad_info.chip_class >= GFX9'), Extension('VK_EXT_display_surface_counter', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_EXT_display_control', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_EXT_debug_report', 9, True), diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ae269c32c49..b49e6d2b2e4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2686,12 +2686,26 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs, pipeline->graphics.cb_target_mask = blend->cb_target_mask; } +static const VkConservativeRasterizationModeEXT +radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo) +{ + const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster = + vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT); + + if (!conservative_raster) + return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; + return conservative_raster->conservativeRasterizationMode; +} static void radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, + struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; + const VkConservativeRasterizationModeEXT mode = + radv_get_conservative_raster_mode(vkraster); + uint32_t pa_sc_conservative_rast = 0; radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, S_028810_PS_UCP_MODE(3) | @@ -2725,6 +2739,39 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0)); + + /* Conservative rasterization. */ + if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { + struct radv_multisample_state *ms = &pipeline->graphics.ms; + + ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); + ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | + S_028804_OVERRASTERIZATION_AMOUNT(4); + + pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | + S_028C4C_POSTZ_AA_MASK_ENABLE(1) | + S_028C4C_CENTROID_SAMPLE_OVERRIDE(1); + + if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) { + pa_sc_conservative_rast |= + S_028C4C_OVER_RAST_ENABLE(1) | + S_028C4C_OVER_RAST_SAMPLE_SELECT(0) | + S_028C4C_UNDER_RAST_ENABLE(0) | + S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) | + S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1); + } else { + assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT); + pa_sc_conservative_rast |= + S_028C4C_OVER_RAST_ENABLE(0) | + S_028C4C_OVER_RAST_SAMPLE_SELECT(1) | + S_028C4C_UNDER_RAST_ENABLE(1) | + S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) | + S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0); + } + } + + radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, + pa_sc_conservative_rast); } @@ -3255,7 +3302,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra); radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend); - radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo); + radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo); radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline); radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline); radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess); -- 2.30.2