From c9dd9b6276f1fe8e729b011ce539bd35c490870a Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 12 Aug 2022 15:46:23 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 13e6c4e44..9f5e9ebb2 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -71,6 +71,16 @@ More than that however it is necessary to fit the usual Vector ISA capabilities onto both Power ISA LD/ST with immediate and to LD/ST Indexed. They present subtly different Mode tables. +Fields used in tables below: + +* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. +* **zz**: both sz and dz are set equal to this flag. +* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) +* **N** sets signed/unsigned saturation. +* **RC1** as if Rc=1, stores CRs *but not the result* +* **SEA** - Signed Effective Address, if enabled performs sign-extension on + registers that have been reduced due to elwidth overrides + **LD/ST immediate** The table for [[sv/svp64]] for `immed(RA)` is: @@ -85,14 +95,6 @@ The table for [[sv/svp64]] for `immed(RA)` is: | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | els RC1 | Rc=0: pred-result z/nonz | -Fields: - -* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. -* **zz**: both sz and dz are set equal to this flag. -* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) -* **N** sets signed/unsigned saturation. -* **RC1** as if Rc=1, stores CRs *but not the result* - The `els` bit is only relevant when `RA.isvec` is clear: this indicates whether stride is unit or element: @@ -144,16 +146,6 @@ The modes for `RA+RB` indexed version are slightly different: | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | zz RC1 | Rc=0: pred-result z/nonz | -Fields: - -* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. -* **zz**: both sz and dz are set equal to this flag. -* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) -* **N** sets signed/unsigned saturation. -* **RC1** as if Rc=1, stores CRs *but not the result* -* **SEA** - Signed Effective Address, if enabled performs sign-extension on - registers that have been reduced due to elwidth overrides - Vector Indexed Strided Mode is qualified as follows: if mode = 0b01 and !RA.isvec and !RB.isvec: -- 2.30.2