From c9e45f01e4f84bce12cd77a3f0ecdb47b8051caa Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 12 Sep 2013 17:49:12 -0400 Subject: [PATCH] config: Add voltage domain to Ruby example scripts This patch adds the minimum required voltage domain configuration to the Ruby example scripts. --- configs/example/ruby_direct_test.py | 13 ++++++++++--- configs/example/ruby_fs.py | 14 ++++++++++---- configs/example/ruby_network_test.py | 13 ++++++++++--- configs/example/ruby_random_test.py | 12 +++++++++--- 4 files changed, 39 insertions(+), 13 deletions(-) diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py index e4d4c73f8..fe96bdc2d 100644 --- a/configs/example/ruby_direct_test.py +++ b/configs/example/ruby_direct_test.py @@ -92,8 +92,14 @@ else: # actually used by the rubytester, but is included to support the # M5 memory size == Ruby memory size checks # -system = System(physmem = SimpleMemory(), - clk_domain = SrcClockDomain(clock = options.sys_clock)) +system = System(physmem = SimpleMemory()) + + +# Create a top-level voltage domain and clock domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) # # Create the ruby random tester @@ -105,7 +111,8 @@ system.tester = RubyDirectedTester(requests_to_complete = \ Ruby.create_system(options, system) # Since Ruby runs at an independent frequency, create a seperate clock -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index 60c4be2b3..ee7a6b33a 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -90,7 +90,11 @@ elif buildEnv['TARGET_ISA'] == "x86": else: fatal("incapable of building non-alpha or non-x86 full system!") -system.clk_domain = SrcClockDomain(clock = options.sys_clock) +# Create a top-level voltage domain and clock domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) if options.kernel is not None: system.kernel = binary(options.kernel) @@ -101,12 +105,14 @@ if options.script is not None: system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] # Create a source clock for the CPUs and set the clock period -system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) +system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, + voltage_domain = system.voltage_domain) Ruby.create_system(options, system, system.piobus, system._dma_ports) # Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) for (i, cpu) in enumerate(system.cpu): # @@ -129,7 +135,7 @@ for (i, cpu) in enumerate(system.cpu): # Create the appropriate memory controllers and connect them to the # PIO bus system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges] -for i in xrange(len(system.physmem)): +for i in xrange(len(system.mem_ctrls)): system.mem_ctrls[i].port = system.piobus.master root = Root(full_system = True, system = system) diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py index b6fdc416f..5a9764d5a 100644 --- a/configs/example/ruby_network_test.py +++ b/configs/example/ruby_network_test.py @@ -104,13 +104,20 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts, # create the desired simulated system system = System(cpu = cpus, - physmem = SimpleMemory(), - clk_domain = SrcClockDomain(clock = options.sys_clock)) + physmem = SimpleMemory()) + + +# Create a top-level voltage domain and clock domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) Ruby.create_system(options, system) # Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) i = 0 for ruby_port in system.ruby._cpu_ruby_ports: diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py index cd1b82f16..203a4b142 100644 --- a/configs/example/ruby_random_test.py +++ b/configs/example/ruby_random_test.py @@ -97,13 +97,19 @@ tester = RubyTester(check_flush = check_flush, # actually used by the rubytester, but is included to support the # M5 memory size == Ruby memory size checks # -system = System(tester = tester, physmem = SimpleMemory(), - clk_domain = SrcClockDomain(clock = options.sys_clock)) +system = System(tester = tester, physmem = SimpleMemory()) + +# Create a top-level voltage domain and clock domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) Ruby.create_system(options, system) # Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) -- 2.30.2